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In this paper, a technique to reduce the output jitter and the wide-range operation is presented. A wide-range voltage controlled delay line (WRVCDL) uses multi-band to operate on wide-range. The proposed DLL operates from 25MHz to 250MHz. An edge combiner (EC) is used to increase the output frequency range. It synthesizes frequencies from 250MHz to 2.5GHz. The output of EC will be a 50% cycle in...
This paper introduces a new bipolar differential pair topology for both gaussian and sinusoidal signal shaping, to be used as a phase-to-amplitude converter alternative in low-power ultra-high-speed DDS. A DDS using this converter, with a 9-bit frequency resolution and an 8-bit amplitude resolution has been designed in a 0.13μm SiGe BiCMOS technology, with ft/fmax of 200/250GHz, and simulated up to...
Due to upcoming power and robustness issues related to decananometer silicon technologies, neuromorphic architectures are increasingly meaningful to perform computation on some specific classes of applications such as signal processing. Such architectures require low-power, compact, and robust hardware spiking neurons. We propose an analog implementation in CMOS 65 nm process of a Leaky Integrate-and-Fire...
A Gm-C frequency-tunable RF bandpass filter is presented. It uses multiple gated transistors (MGTR) to improve transconductors linearity, limiting noise degradation and power consumption. This leads to a high dynamic range. The design uses CMOS 65nm and stands as a good alternative to fully integrate the RF selectivity of silicon TV tuners over VHF bands (45–470MHz).
The paper describes the efficient CMOS technology based current source for system identification and it's layout realization with reduced circuit complexity. Square wave excitation current is preferred in energy constrained and embedded environment. It has been shown that by shortening the square waves, spectral purity of the excitation signals can be drastically improved. Further improvement can...
Stochastic decoding that is inspired by stochastic computation is an alternative technique for decoding of error-correcting codes. The extension of this approach to decode convolutional codes and turbo codes is discussed in this article. The switching activity sensitivity is circumvented and the latching problem is reduced by transforming the stochastic additions into stochastic multiplications in...
In this article, a new methodology for mapping applications onto matrix-based nanocomputer architectures is proposed. It takes into account the structural characteristics and connectivity restrictions of cell matrices and can be used (i) for the partitioning and mapping of applications, (ii) for the generation of alternative mapping configurations with required area, power and delay characteristics...
In this paper, we propose an architecture for FPGA-implementation of neural adaptive neural network RF power behavioral modeling. The real-valued time-delay neural network (RVTDNN) and the backpropagation (BP) learning algorithm were implemented on FPGA using Xilinx System Generator for DSP and the Virtex-6 FPGA ML605 Evaluation Kit. Performances obtained with 16-QAM modulated test signal and material...
The problem of estimating the exact shape of the glottal flow derivative (GFD) using reweighted 1-norm minimization of the second derivative of the GFD is addressed in this paper. By using physiological models of the glottal flow derivative, such as the Liljencrants-Fant (LF) and Rosenberg models, it is intuitively found that the second derivative of those models is highly sparse. Based on this observation...
The ever increasing demand for low power DSP applications has directed researchers to contemplate a variety of potential approaches in different contexts. In this regard, using some alternative number systems, which inherently are capable of reducing the hardware complexity, have been propounded. In this work, a 2DLNS-based platform for multiplication intensive DSP applications is presented. Implementing...
The ultimate goal of this work is to identify a methodical analysis of imager design to achieve high level of flexibility and modularity. It will enable early stages of design space exploration using hierarchical approach. In particular, we develop generic models for imager IC in order to explore early design choices throughout the hierarchy. This modeling approach supports top-down design flows.
In a context of high performance low power integrated vision system design, a methodology based on the exploration of many architectural and algorithmic issues, relying on analog pre-processing of low-resolution images, is considered. In this paper we present the algorithm exploration performed for analog coarse motion detection and the corresponding SystemC model developed for coupling with a digital...
In this paper we present a new readout technique designed for CMOS logarithmic image sensor. It provides also an implemented motion detection scheme useful for many applications especially those of surveillance. The main purpose of this work is to reduce power dissipation and time waste due to the readout of a huge amount of redundant data outgoing from the sensor through analog to digital converter...
A new methodology to automatically extract features from mammograms is presented. The approach is based on a combination of the discrete wavelet transform and the Gabor filter, and it can be easily implemented in a breast cancer screening system. First, the two-dimensional discrete wavelet transform is employed to process the mammogram and obtain its HH high frequency sub-band image. Then, a Gabor...
A low current front end trans-impedance amplifier (TIA) switching bank for multi-spectral photodiode (PD) arrays is presented. The design mitigates PD capacitance effects by using a gm-boosted input common-gate stage. Simulation results show that a bandwidth of 97 MHz can be reached with a maximal gain of 7.53 MΩ with a tuning range of 24 dB. The system is suited to low PD currents as its total input...
Novel CMOS technologies are rapidly migrating towards the nanometer world. The design and optimization of complex analog circuits employing these processes is impracticable when using only transistor-level electronic design automation (EDA) tools. Efficient design methodologies including behavioral modeling are inevitable, but the high-level models should incorporate accurate circuit characteristics...
With the advent of increasingly higher numbers of processors on-chip, task scheduling has become an important concern in system design, and research in this area has produced substantial and diversified knowledge. As a result, the efficient management and taping of this knowledge has become a concern in itself. This paper addresses the issue of how to effectively extract performance information about...
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