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To enable three-dimensional (3D) ASIC and memory integration, large-size silicon interposer is a critical technology [1]. Currently most silicon interposers are manufactured by wafer foundries and are limited in size by the wafer lithographic processing. In this study, manufacturing of cost- and performance-effective, large-size silicon interposers are investigated. The existing supply chain and infrastructure...
There has been a great discussion about electro-migration behavior in semiconductor area. And it has been often discussed that electro-migration behavior of the flip chip package using Sn-Ag bump. However, little study has been done to explore the electro-migration behavior of low temperature solder such as a Sn-Bi solder. In this report, we investigated electro-migration behaviors of micro pillar...
Influence factors of warpage change during assembly process for 2.5D package using silicon-interposer were investigated. Mechanical properties of organic substrate have the dominant influence. In contrast, material properties of U.F. material have little impact.
In order to achieve high speed transmission and large volume data processing, large size silicon-interposer has been required. Warpage caused by the CTE mismatch between a large silicon-interposer and an organic substrate is the most significant problem. In this study, we investigated several warpage control techniques for 2.5D package assembly process. First was assembly process sequence. One is...
To achieve high density and high speed transmission between chips, a silicon interposer with copper (Cu) Through Silicon Vias (TSVs) technologies have been required. In previous papers, we reported process development and integration with 200mm wafer. It has been shown that high aspect ratio TSVs were filled with Cu without any voids. Delamination of dielectric layers did not occur on both side of...
As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer approach combined with 3D integration technologies opens new possibilities in advanced packaging. Especially for high end applications where several processor needs to communicate together, this approach could enhance the performances of whole systems...
In this report, we investigated electro-migration behavior of two types of low temperature bonding. One was Sn-57 Bi using conventional C4 process. The other was Au-In Transient Liquid Phase bonding (TLP). Electron flow to induce the electro-migration was from substrate side (Ni pad) to chip side (Cu post) with current density of 40000A/cm2 at 150 degree C. In the case of Sn-57 Bi conventional C4...
In order to realize high-performance LSI systems, a Si interposer with Cu filled through silicon vias (TSVs) and a low inductance decoupling capacitor was developed in this work. We fabricated a thin film capacitor (TFC) on the Si interposer and evaluated its properties. Capacitance density of the TFC achieved 2uF/cm2. Temperature coefficient of capacitance (TCC) was under 15% (25–125 deg C). The...
The silicon interposer had been desired to have high Imput/Output (I/O) counts and fine wirings such as the global wiring of devices. High integration of several chips on the silicon interposer will realize a high performance silicon module same as System on Chip (SoC). We previously reported the fabrication process of TSVs and fine Cu wirings on a silicon interposer and the results of reliability...
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