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Plastic packaging has made successful progress in replacing ceramic and metal packages in many high reliability electronics applications where hermetic packaging has traditionally been used, e.g. military and aerospace semiconductors. However for high voltage/high current power devices, such as the thyristors and diodes used in High Voltage Direct Current (HVDC) power transmission applications, hermetic...
This paper presents a research focused on development of an advanced screen printing technique for the fabrication of miniaturized, low-cost organic humidity sensors. According to the survey done by BCC Research the segment of temperature and humidity sensors achieved a worldwide turnover of 3.7 billion USD in 2010 and it represented 7 % of global sensor market [1]. Humidity sensors based on organic...
This paper deals with the research and development of high density interconnection (HDI) substrates and passive components embedded into HDI substrates. Both HDI substrates and passive embedded components are fully formed by the photolithography method. The manufacturing process consists of screen printing process used for individual layers deposition and photolithography process for all layers structuring...
A reflection-mode photoplethysmographic (rPPG) patch probe has been researched to improve its performance for non-invasive physiological assessment through electrically conductive adhesives (ECAs) based manufacture processes. Special PiN photodiodes and Light Emitting Diodes (LEDs) were mounted on a flexible printed circuit to reach the objectives of both sensitivity and stability, and user comfort...
In this paper, we demonstrate that crossed multimode graded-index (GI) optical waveguides show very low crossing loss. We actually fabricate multiple-perpendicularly-crossed waveguides with GI core (WG2), and quasi-GI waveguides (WG1) that have a GI profile only in the horizontal direction while a step-index profile in the vertical direction, and then compared with the SI core crossed waveguides (WG3)...
To meet the increasing lifetime requirements of solder joints in thermal cycling, the coefficient of thermal expansion (CTE) of the printed circuit board (PCB) has to be conformed to the CTE of the surface mounted devices (SMD). Novel reinforcing fabrics were successfully used to reduce the CTE of the PCB. Thereby, the mismatch in the CTE of PCB and SMD was reduced. In order to check the expected...
With the current development of IC technology nodes becoming “Moore-than-Moore” challenging, industry and research institutes such as Imec are increasing their focus to come up with solutions to these challenges. A solution closely followed at the moment is the development of 3D ICs and 3D packaging. In developing these technologies, there are quite a lot of complexities involved. The development...
The investigation of the bonding pressure change on the different quality aspects of the solid-liquid interdiffusion (SLID) interconnects is presented. The stacks were produced by a flux-assisted bonding of two Si dies with an area array of square Cu/SnAg bumps on the bottom die and Cu bumps on the top die at approx. 250 °C. The bonding pressure was varied between 0 MPa, 0.35 MPa, 0.69 MPa, 1.04 MPa,...
In this work, diamond nano-particles doped Sn-8Zn-3Bi solder alloys have been studied. The microstructure and the interfacial reactions of the plain solder joints and solder joints containing diamond nano-particles were investigated under current density of 5×103 A/cm2 at temperature of 100°C with Cu pads on daisy chain type ball grid array (BGA) substrates. It was found diamond nano-particles doped...
Most of the challenges for Cu-Cu bonding are bump co-planarity, surface roughness, thermal budget, and interface bonding quality. Normally the process needs high bonding temperature, pressure, and long bonding time. Regarding bump co-planarity, several options are considered, including plating optimization, CMP planarization, fly cut, and bump reflow. In this work we have demonstrated that bump co-planarity...
3DIC integration has been well know as the next generation of semiconductor technology with the advantages of small form factor, high performance, low power consumption, high density integration, etc. The stacked assembly is one of the key enabling technologies to perform 3D integration. One popular approach to achieve intrinsic metal interconnect is stacked bonding by lead-free solder bumps. With...
Due to increased demands for the integration density of electronics, a turnaround in packaging technology has taken place, away from packaged constructions towards chip-onboard technology. A particular challenge of this technology is the avoidance of chip fracture during processing and subsequent use. In the present study a method was worked out which combines the two relevant factors for chip fracture...
Manufacturing-induced thermal stress created during the fabrication of packaged integrated circuits can potentially lead to device failure. Therefore, the need to develop metrologies that can be used to effectively measure stress/strain in systems-on-chip or systems-in-package is identified by the International Technology Roadmap for Semiconductors (ITRS). In this study, a novel technique for non-destructive...
This paper presents copper filling of TSV using an acidic cupric methanesulfonate electroplating electrolyte containing chloride and a poloxamine suppressor. The process was accomplished utilizing a single component suppressor system. Such a plating system might simplify the additive replenishment procedure during the TSV filling. The influence of the poloxamine on the copper deposition was also investigated...
Recent technological breakthroughs in Micro-Electro-Mechanical Systems (MEMS) technologies have enabled significant cost reductions of MEMS gyroscopes and they are being increasingly employed in new application areas such as portable consumer electronics. Reliability assessment of MEMS assemblies is, however, more challenging than that of conventional IC assemblies: reliability characterization of...
Conventional Deep Reactive Ion Etching (DRIE) is a plasma etch process with alternating half-cycles of 1) Si-etching with SF6 to form gaseous SiFx etch products, and 2) passivation with C4F8 that polymerizes as a protecting fluorocarbon deposit on the sidewalls and bottom of the etched features. In this work we report on a novel alternative and disruptive technology concept of Spatially-divided Deep...
The Filling of high aspect ratio through silicon vias (TSVs) using copper plating without any void or seam is one of the technical challenges for 3D integration. This paper presents numerical simulation and experimental verification of copper plating with different additives and a guideline for process optimization is proposed. Theoretical models are derived and a generic calculating approach is developed...
Reliability of electro-technical products is still a highly actual and discussed topic. Every electro-technical product consists not only of the components, functional blocks and systems, but also substrate as printed circuit board (PCB) or ceramic substrates, which are interconnected by solder joints. This article is focuses on a comparison of some properties of solder joints on ceramic and PCB substrates...
Many transmission lines discontinuities such as cracks, short connections and changes of the conductive line width can create during printed circuit boards manufacturing. There are different methods for detection of these discontinuities on printed circuit boards (electrical and optical test methods) [1]. Unfortunately, these detection methods are not universal and particular methods do not detect...
The aim of the presented work is to study de behavior of through hole technology capacitors under extreme thermal stress conditions, both under static high temperatures and relatively fast temperature cycling during soldering processes. In consequence, aluminum electrolytic, ceramic and plastic film capacitors were subjected to a series of thermal experiments, in order to compare their behavior and...
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