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A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise,...
This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that the SNDR penalty introduced by this effect can become significant at high frequencies. To address this issue, a passive resonant clock network is proposed to distribute the clock to the comparators in a flash ADC. The inductive termination of this network serves to resonate out the parasitic and input capacitances...
A discrete-time, switched-capacitor, MASH 2–2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth...
In a digital control system for magnetic bearings, because of factors such as switching currents of a power amplifier, an input signal of the system will be mixed with noise and the signal should be filtered. If the sampling rate of the system for the input signal is not high enough, a filter used will introduce a large delay between its output and input signal. To solve this problem, one way is to...
With the technology nodes keep advancing, the application of TSV(Through Silicon Via) technology in 3D integration is faced with more challenges. The shift from via-last to via-middle fabrication scheme, the ever-increasing density of TSV, the reduction in supply voltage and the increase in frequency of on-chip local clock, all pose threat to signal/power integrity of the TSV system. In this paper,...
This paper presents an effective design approach for the power supply filter of a phase lock loop (PLL) based clock generator in a multi-core ASIC. The noise sensitivity of different types, filter design, system design issues, and measurement techniques for verification and understanding of jitter behavior on power supply noise are discussed.
This paper introduces a leakage model in the frequency domain to enhance the efficiency of Side Channel Attacks of CMOS circuits. While usual techniques are focused on noise removal around clock harmonics, we show that the actual leakage is not necessary located in those expected bandwidths as experimentally observed by E. Mateos and C.H. Gebotys in 2010. We start by building a theoretical modeling...
This paper solves the problem of time synchronization in wireless sensor networks (WSNs) with noise. The consensus based approach is an improved average value based protocol. This algorithm, compared with the existing consensus-based synchronization approach, has the advantage of being totally distributed, asynchronous and robust to process and measurement noise. The main idea of this algorithm is...
The speed of general purpose input output (GPIO) continues to increase as more consumer applications utilize “smart” devices. The low-voltage differential signaling (LVDS) is often times the highest speed that GPIO interface needs to support in the mixture of different single ended signaling pins. Although LVDS is differential and somewhat immune to direct signal coupling from other signals, it is...
In this work, the authors demonstrate Core-type and IO-type on-die noise characterization to enhance CPU PDN (Power Delivery Network) performance in microprocessor. The two representative power supply noise characteristics are simulated using excitation models and an impedance modeled of the power delivery network. Then, the design metrics for the PDN are analyzed based on excitation. Behavior of...
Decoupling core power for modern processors or SOCs is a challenging task due to large power consumption. The decoupling network designed by a commonly used target impedance approach is known to be very pessimistic and very difficult to implement. In this paper, a step surge current is identified as a major source of core power noise. By considering the ramp time of the surge current, we propose a...
Power supply induced clock jitter accumulation is a function of several variables including the power supply rejection characteristics of circuits in the signal path, signal path electrical length, signaling frequency, and voltage supply noise magnitude and frequency. Brute force, closed-loop, transistor-level modeling and simulation of clock timing in the presence of an extracted power delivery network...
Jitter is a crucial factor in high speed and high performance ADC testing. This paper proposes an efficient and accurate jitter estimation method based on one frequency measurement. Applying simple mathematical processing to the ADC output in time domain, the RMS of jitter and noise power are obtained. Furthermore, prior information of harmonics does not need to know before the processing. The algorithm...
Despite the widespread use of Bluetooth technology, identity management of Bluetooth devices remains a significant challenge because the MAC address and name of Bluetooth device are easy to forge. In this paper, we present BlueID — a practical system that identifies Bluetooth devices by fingerprinting their clocks. Previous approaches to clock fingerprinting exclusively rely on the timestamps carried...
Onera has been developing quartz based MEMS inertial sensors for long, including for some years the associated digital electronics. Direct Digital Synthesis (DDS) and computerised control loops have been introduced as a replacement for self-sustained oscillators and analog PLL. However, the design parameters of digital synthesisers (word length of phase accumulator, size of Look Up Table, number of...
The National Aeronautics and Space Administration (NASA) Cyclone Global Navigation Satellite System (CYGNSS) mission aims to understand the coupling between ocean surface properties, moist atmospheric thermodynamics, radiation, and convective dynamics in the inner core of tropical cyclones (TCs). The mission is comprised of eight microsatellites (μSats) in low-earth orbit (LEO) at an inclination of...
In advanced applications such as satellite telecommunications, digital radar, frequency hopping data links and micro-wave communications, powerful signal processors able to handle broadband signal vectors are becoming more common. The bottleneck is now the availability of high sampling rate and high linearity data converters, ADCs (Analog to Digital Converter) for reception and DACs (Digital to Analog...
In wireless medium, requirement of high frequency is increasing day by day. For high frequency based system data rates should be high. In unguided media, as signal travels a long distance and due to interference of noise, there is error in phase and frequency and we get a deviated output. In view of this, We are motivated to design a low power frequency synthesizer which would provide a low locking...
In this paper, a low power differential biopotential amplifier (BPA) targeted for front-end electroencephalogram (EEG) signal amplification is reported. The proposed BPA is chopper stabilized to minimize flicker noise or 1/f noise, improving the fidelity of the signal measurement. This work aims to provide a low power BPA design solution for portable EEG application. This work proposes a non-overlapping...
In this paper a comparison of analog versus digital information is given, where the superior noise resilience of digital signals is shown to necessitate digital signalling for modern high-speed signaling environments. Non-idealities that are analog in nature are shown to necessitate ADCs in the digital signal path, which allow for signal recovery in the digital domain. A brief discussion of the Flash...
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