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In this work, we propose a novel packaging concept for highly-integrated RF systems using a magnetically aligned Z-axis anisotropic conductive adhesive. We demonstrate the ability to ldquogrowrdquo interconnects allowing for multilayer packages that are not sensitive to the height between pads. Using this effect we introduce two approaches to integrating multiple silicon wafers on top of each other,...
Three dimensional numerical simulations were performed to investigate a novel high efficiency back contact solar cell design with a selective emitter. The effect of several physical parameters (bulk lifetime, substrate doping, emitter fraction and surface recombination velocity in the gap between the emitter and BSF) on solar cell performance is explored using the SENTAURUS DEVICE?? program (formerly...
We develop a back contact monocrystalline thin-film silicon solar cell using the porous silicon process. Laser processes are applied for all structuring steps. Thus no photolithography or other masking techniques are required. A single evaporation step is used to metallize the cell. Laser scribing is used for contact separation. The cell has a planar front surface, an area of 79.2 cm2 and a cell thickness...
A new approach for the fabrication of large contour-mode single-crystal silicon resonators has been demonstrated without the use of SOI substrates. 24-MHz-disk resonators have been built thanks to industrial facilities dedicated to the integration of passive components on silicon. They exhibit a good compromise between the quality factor Q higher than 50000 and the motional resistance of a few kilo-ohms.
With the demands of miniaturized solutions that are able to handle increased heat dissipation, the use of silicon substrates with through-silicon vias (TSV) in electronics modules becomes more and more interesting. Shorter signal path, better cooling of tracks, better impedance control and smaller foot-prints are some of the advantages. This also avoids some RC delays of long, in-plane interconnects...
We discuss the use of electron-shading effect during the plasma-enhanced chemical vapor deposition to control the growth of carbon nanotubes (CNTs). We designed and fabricated the trench and island test structures. The horizontally aligned CNTs were grown from the sidewall of the polysilicon structure, parallel to the silicon oxide surface. We investigated the electrical property of the CNT number...
PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch...
A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were...
We have demonstrated multi-walled carbon nanotube (MWCNTs) based sensors, which are capable of detecting alcohol vapor. The properties of the sensor were as a function of baking times at ethanol flow rate 200 cc/min and nitrogen gas flow rate 200 cc/min. Moreover, the various of baking times were observed that the highest sensitivity was obtained at baking time of 25 minutes at 70??C can be explained...
We use infrared microscopy to image the temperature profile of graphene field-effect transistors operating at constant source to drain current bias. We find a peak in the temperature profile, i.e. a ??hot spot?? appears near the drain (anode) electrode of the graphene sheet at high current while operating in the hole-doped regime. We shift the hot spot position on the graphene sheet by tuning the...
In order to study the electrical contact property at metal film interfaces, a NiCr/TiW film of about 40 nm/30 nm were deposited on the silicon substrate by magnetron sputtering. The mechanical and electrical properties of the film were studied by nano-ECR system. Different loads from 1500 muN to 3500 muN with voltage of 5 V were applied to the sample. Changing of the electrical property in NiCr/TiW...
Chip to substrate interconnect density is continuously being scaled down to support the rapidly decreasing minimum feature size of IC components. At very fine interconnect pitches not many chip to substrate interconnects can meet the requirements of reliability and performance. One potential solution to improve the interconnect reliability is the use of compliant structures as interconnects. In this...
Flip chip technology is now being introduced in PoP(Package on Package) packages for the digital consumer electronics such as digital still cameras and mobile phones. PoP reduces the component height and improves the electrical performance. A MPS-C2(Metal Post Solder Chip Connection) method was developed for ultrafine pitch flip chip interconnections in mobile applications. A bare die with Sn/Ag-solder-capped...
As operating frequencies increase in state-of-the-art wireless designs, highly accurate modelling of critical interconnect paths routed over silicon is crucial for first-pass design success [1]. With this in mind, the interconnect stack of an IBM silicon germanium (SiGe) process incorporating a TSV ground supply network was modelled with model accuracy and efficiency as the goals. A unique modelling...
This paper reviews special RF/microwave silicon device implementations in the back-wafer contacted Silicon-On-Glass (SOG) Substrate-Transfer Technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed...
Simulation and physical experiments have shown that vacancy engineering implants have the potential to provide outstanding pMOS source/drain performance for several future CMOS device generations. Using vacancy-generating implants prior to boron implantation, hole concentrations approaching 1021cm-3 can be achieved using low thermal budget annealing. In this new study we propose that the vacancy engineering...
Selective emitter formation in silicon based solar cell is recently becoming a common technique to enhance the blue response of solar cell. In this work, we suggest a novel procedure based on a self alignment thought to overcome the realignment problems that still limit its industrial request. The idea is based on a plasma dry etching procedure of the emitter region using the metal grid of the cell...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
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