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An externally static, internally dynamic topology creates a new logic family that enables the user to tune effective transistor thresholds post-fabrication by adjusting a few power supplies. These gates can therefore be programmed for higher speed or for lower power based on the system requirements. An application of this logic to programmable interconnect circuits is shown in this paper. In a 90-nm...
Fuzzy theory applications have been explored and analyzed on fields as pattern recognition, control, data classification, signal processing, expert systems, among others. To accomplish this, more complex calculations and faster processing speed are required, turning fuzzy hardware implementation to be the perfect choice. Fuzzy operations as t-norms and t-conorms are used in fuzzy systems as conjunction...
Energy-performance tunable circuits enable the user to adjust the energy and performance of a chip after fabrication to suite the particular application, thus increase the overall power efficiency of the chip. Two tunable interconnect architectures are proposed. Pseudo-static interconnect achieves the same performance as static interconnect while consuming only 65% as much energy and provides 2X wider...
Two complementary techniques for reducing the effect of within-die variability on the critical path delay in FPGA circuits are reported. The first technique selects the best LUT mapping from a set of alternative mappings of a logic function for each LUT cluster in the FPGA. The second selects the best assignment of LUTs to physical locations within a cluster. The techniques can be used together, and...
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. This paper presents a method for symmetrical FPGA placement based on ant colony optimization (ACO). Also, we take the routing congestion into consideration by introducing a congestion factor in our algorithm. Experimental results show that compared with the state-of-the-art FPGA...
Many n-D signal processing applications require realization in real time. We propose the realization of a 3-D spatio-temporal wave digital filter (WDF) in an FPGA. Optimization of the implemented hardware architecture includes evaluation of two different kinds of overflow handling, namely by saturation and a ldquomodulo 2rdquo type operation. The FPGA board is processing DVI signals that can be provided...
To accommodate large designs, existing 2D Field Programmable Gate arrays (FPGA) may not be sufficient. In such scenarios, 3D FPGAs will be useful. Our Algorithm makes use of Auction Based Methodology to solve the detailed routing problem in case of 3D FPGAs.
In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-case delay. In particular, we developed an efficient logic optimization operation ldquobalancerdquo and a library mapping algorithm named BTWLibMap. Together they are able to reduce the probability of a timing error by 2.3X while only incurring...
The development of a multi-cycle hardware design of a time-varying (TV) filtering system, suitable for real-time implementation on an integrated chip is outlined in this work. Based on results of time-frequency (TF) analysis and the instantaneous frequency (IF) estimation, the proposed design enables multiple detection of the local filter's region of support (FRS) in the observed time-instant, resulting...
The principle of duplication and comparison has proven very efficient for error detection in processor cores, since it can be applied as a generic solution for making virtually any type of core fail safe. A weakness of this approach, however, is the potential for common cause faults: Faults affecting both cores in the same way will escape detection. Shared resources and signals are especially prone...
Decimal multiplication is an integral part of financial, commercial, and Internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency...
Carbon nanotube field effect transistors (CNFETs) are already competitive in some respects with state-of-art silicon transistors, and are promising candidates for future nano-electronic devices. The ability of CNFET for using high K-dielectric provides high insulator capacitance which improves the gate control and also lowers gate leakage. This paper proposes new energy efficient CNFETs based drivers...
The limitation of speed of modern computers in performing the arithmetic operations such as addition, subtraction and multiplication suffer from carry propagation delay. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). We proposed fast adders based on Quaternary signed digit number system. In QSD, each digit can be represented...
In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp a periodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters is implemented on a...
In this paper presents a low power communication circuit design using selective glitch removal method. A given Boolean network has to be represented to DAG. The proposed method consists of four steps. In the first step, TD (transition density) calculation has to be performed. Total power consumption is obtained by calculating switching activity of each node in a DAG. In the second step, the feasible...
To ensure security and robustness of the next generation of Physically Unclonable Functions (PUFs), we have developed a new methodology for PUF design. Our approach employs integration of three key principles: (i) inclusion of multiple delay lines for creation of each response bit; (ii) transformations and combination of the challenge bits; and (iii) combination of the outputs from multiple delay...
Due to rapidly growing system-on-chip industry, not only the faster units but also smaller area and less power has become a major design constraint for VLSI community. Further, demand for high speed is continuously increasing. In processors, most commonly used arithmetic operation is the addition operation. It is the adder delay that determines the maximum frequency of operation of the chip. Different...
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (observability don't care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB (branch target buffer) and 4-way set associative cache using pseudo LRU (least recently used) algorithm...
This article reports the first results on fast and accurate power evaluation in arithmetic operators. The proposed method uses two steps: 1) accurate useful activity evaluation, 2) fast glitching activity estimation. The first step is based on circuit emulation using FPGA. Activity counters are inserted into the low-level description of the evaluated operator. The modified description is synthesized...
In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture,...
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