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High level synthesis (HLS) is the field of transforming a high level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, binary synthesis is a method for synthesizing existing compiled applications for which the source code is not available. One of the advantages of FPGAs over software is the availability of multiple memory banks. Until now, binary...
Carry chains are a standard feature of modern FPGA architectures. They enable compact, regular and yet very fast implementations of the binary word addition even outpacing sophisticated parallel prefix networks for bit width far beyond 100. Although they are equally suited for other simple prefix computations, their employment in the implementation of such user functions is hindered by unportable...
This paper investigates the challenges of run-time resource management in future coarse-grained network-on-reconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature expected in future processing systems which must support multiple applications whose processing requirements are not known at design time. This paper investigates a stochastic routing algorithm in a NoC-based system with...
Dynamic reconfiguration is a powerful approach for realizing a high-speed and low-power-consumption system. It enables a system to gather as much specific circuits as the system requires, and then to comprise general-purpose computation. This paper introduces a real-time video-streaming processing system with dynamic reconfigurations. In our case studies, our system achieved high performance (4times...
This paper presents a novel method of reducing the spurious signal content in a digitally synthesized sine wave at the output of a numerically controlled oscillator (NCO). The proposed method uses a linear approximation subsystem with a reduced size look-up table (LUT). Two NCO architectures are considered. Architecture 0 - which is the standard - in which the accumulator word length is longer than...
An important biology problem is the decoding of the DNA and the extraction of useful genetic information. There are many bioinformatics algorithms that try to solve the gene finding problem and one of the most efficient is the Glimmer algorithm. In this paper, we present a hardware architecture that implements the Glimmer algorithm. The architecture was developed specifically for the capabilities...
Random number generators play an important role in the field of cryptography and security. It is often required that a random number generator consists of digital logic blocks only, so that it can be implemented on reconfigurable platforms. Since randomness cannot be proved by statistical tests there is a need for a provably secure hardware random number generator. In order to provide a proof of security,...
The paper presents a new efficient method for implementation of the AES byte substitution function (S-box). It is aimed at the AES implementation in non-volatile FPGAs featuring volatile embedded RAM blocks. The method uses a pair of linear feedback shift registers to generate substitution tables into embedded RAMs. The proposed solution requires less space and is faster than the one implementing...
This paper presents CREMA, a coarse-grain reconfigurable array with mapping adaptiveness. Mapping adaptiveness consists of tailoring the array to a specific application requirements. Run-time reconfigurability allows the re-usage of same PE with different functionality and interconnections among the ones supported. We proved this approach very efficient if compared with a standard CGRA. In our test...
Self-organization is a natural concept that helps complex systems to adapt themselves autonomically to their environment. In this paper, we present a self-organizing framework for multi-cue fusion in embedded imaging. This means that several simple image filters are used in combination to lead to a more robust system behavior. Human motion tracking serves as a show case. The system adapts to changes...
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run efficiently, as compared to a general-purpose computer. This paper presents an architecture that benefits from the large number of DSP modules in Xilinx technology to implement massive floating point arithmetic. Our architecture...
This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for exploring design spaces suffer from expensive computation time, which is exacerbated by increased dimensionality due to the larger number of architectural parameters. In this paper we build on previously published work to describe...
This paper presents a time-to-digital converter based on Virtex FPGA's reconfiguration and phase shifting capabilities. Concretely, the converter is built around a Digital Clock Manager, and phase shift is the module's characteristic that is modified through reconfiguration. The proposed conversion method shifts an internally generated clock signal's phase to precisely determine the position of a...
Many high-performance applications involve large data sets that are impossible to fit entirely within on-chip memories of even the largest FPGAs. As a result, they must be stored in off-chip SDRAMs and loaded onto the FPGAs as computations progress. Because of the high latency and energy consumption associated with off-chip memory accesses, it is important to develop efficient operation schedules...
This work introduces an FPGA implementation for vessel tree extraction on retinal images. The retinal vessel-tree can be used in disease diagnoses, e.g. diabetes, or in person authentication. In such cases, a portable device with a high performance may be a need. The FPGA implementation discussed here, although application-oriented, features a fully programmable SIMD architecture, allowing for an...
Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and verified intellectual property (IP) cores. This paper presents CHREC XML, a XML schema that facilitates IP reuse by encapsulating the details of reusable IP cores at multiple levels of abstraction. This schema is independent from...
The susceptibility of digital systems to tampering is of immense concern to military and commercial organizations. Current defenses against such techniques as reverse engineering and side channel analysis are limited and don't address the underlying vulnerable characteristics of digital circuits. In this paper, we propose a generalized defense methodology named dynamic polymorphic reconfiguration...
This paper presents a new single event upset (SEU), multiple bit upset (MBU) and single hardware error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional triple module redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable...
Field Programmable Gate Arrays (FPGAs) inherent reconfigurable nature and their low power consumption have made them so complementary to microprocessors that many are advocating their inclusion in all supercomputing clusters. Today FPGAs are included in few mainstream computer systems for accelerating application specific performance. Among the numerous areas in reconfigurable computing FPGA have...
This paper presents an FPGA-friendly approach to tracking elephant flows in network traffic. Our approach, single step segmented least recently used (S3-LRU) policy, is a network traffic-friendly replacement policy for maintaining flow states in a Naiumlive hash table (NHT). We demonstrate that our S3-LRU approach preserves elephant flows: conservatively promoting potential elephants and evicting...
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