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This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (observability don't care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB (branch target buffer) and 4-way set associative cache using pseudo LRU (least recently used) algorithm...
We have designed an SoC platform with a multi-channel bus architecture which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of OpenRISC 1200 processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral...
We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of RISC processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows...
This paper describes the development of a synthesizable SoC platform using OpenCores processor and WISHBONE on-chip bus. The platform includes a OpenRISC 1200 microprocessor, some basic peripherals, such as on-chip RAM, GPIO, UART, debug interface, VGA controller and WISHBONE bus and uses the set of development environment including compiler, assembler, debugger that is built for system debugging...
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