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The following topics are dealt with: message passing interface; multiCPU system; graphics processing unit; FPGA register allocation; reconfigurable architecture; low power management; image processing; fault tolerance; circuit reliability; network-on-chip interconnect; cryptography; watermarking; IP protection; and video signal processing.
In order to meet ever-increasing computing needs and overcome power density limitations, the computing industry has halted simple processor frequency scaling and entered the era of parallelization, with tens to hundreds of computing cores integrated in a single processor, and hundreds to thousands of computing servers connected in a warehouse-scale data center. However, such highly parallel, general-purpose...
In an engineering perspective, agility is one property that a designer must consider when creating a product that is expected to undergo change throughout its lifetime. For embedded computing systems, traditionally the system hardware is fixed, and the system software provides the means of achieving agility. Altering software functionality is relatively easy to do, and software compile times are fast...
As integrated circuit fabrication processes continue to provide exponential increases in density of transistors with each generation, the question of what to do with those transistors becomes ever more interesting. The most fundamental part of that question is the global organization of the structures created from the transistors, most commonly referred to as the *architecture* of the device. Most...
FPGA companies are amongst the earliest adopters of next-generation process technology. This involves many challenges, including power management, device modeling, increasing I/O performance to match the computational capacity, and enabling very large designs to be completed quickly. Process scaling increases FPGA capacity and allows new features, such as high-performance I/O protocols (e.g. PCI Express)...
Summary form only given. Recently, Xilinx introduced two new FPGA families, Virtex-6 and Spartan-6, closely related in architecture, but each optimized for different markets and applications: Virtex-6 for high performance, features and capacity; Spartan-6 for low cost and low power consumption. Both families take advantage of 40/45 nm technology, and both are derived from the successful Virtex-5 architecture...
MuCCRA-cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90 nm CMOS process consisting of four dies each of which has a 4 times 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and...
Message-Passing is the dominant programming model for distributed memory parallel computers and Message-Passing Interface (MPI) is the standard. Along with point-to-point send and receive message primitives, MPI includes a set of collective communication operations that are used to synchronize and coordinate groups of tasks. The MPI_Barrier, one of the most important collective procedures, has been...
As FPGA based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these systems. Previous work has demonstrated that support for multithreading in soft processors can tolerate pipeline and I/O latencies as well as improve overall system throughput-however earlier work assumes an abundance of...
Biophysically accurate neuron models have emerged as a very useful tool for neuroscience research. These models are based on solving differential equations that govern membrane potentials and spike generation. The level of detail that needs to be presented in the model to accurately emulate the behaviour of an organic cell is still an open question, although the timing of the spikes is considered...
Convolutional networks (ConvNets) are biologically inspired hierarchical architectures that can be trained to perform a variety of detection, recognition and segmentation tasks. ConvNets have a feed-forward architecture consisting of multiple linear convolution filters interspersed with pointwise non-linear squashing functions. This paper presents an efficient implementation of ConvNets on a low-end...
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in...
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems is the scheduling and allocation of the tasks on the reconfigurable fabric. In this paper we present a two level scheduling mechanism for tightly coupled reconfigurable architecture machines. To overcome the complexity of...
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