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A decoder is a hardware module that expands an x-bit input into an n-bit output, where x ?? n. It can be viewed as producing a set P of subsets of an n-element set Zn. If this set P can be altered by the user, the decoder is said to be configurable. In this paper we propose a class of configurable decoders (called ??mapping-unit?? based decoders or simply MU-decoders) that facilitate efficient selection...
Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event...
With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/SOP reconfigurable design style to exploit both the advantages of LUT-cell and SOP-cell for circuit design...
The Wave Dynamic Differential Logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail signals in WDDL design....
Field programmable gate arrays (FPGAs) allow the same silicon implementation to be programmed or reprogrammed for a variety of applications. It provides low NRE (non-recurring engineering) cost and short time to market. As CMOS technology continue to scale down to nanometer, increased power consumption and worsened process variation become crucial constraints for FPGAs. The survey reviews the process...
This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated...
Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured...
This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via...
FPGA structures are widely used due to early time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of signals in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In...
This work presents Adaptive Vgs Multiplexer (AVGS-Mux) Technique. Proposed method controls the transistor current by the source voltage. It can provide ??1.6X control on the delay and ??7X exponential control on sub-threshold and gate leakages in the switch-box, LUT, and interconnects. For equal leakage, it improves the speed 9%, reduces dynamic power 13%, and reduces random dopant fluctuations effect...
There is a continuously increasing demand for lower power consumption and higher operating frequencies in digital systems. In addition, external or operation-induced disturbances may significantly affect circuit functionality or performance. This paper analyzes the effect of power supply disturbances on the propagation delays of digital circuits implemented in Spartan-3A FPGAs and demonstrates that...
The Wave Dynamic Differential Logic (WDDL) is a promising countermeasure to protect cryptographic devices from Differential Power Attacks (DPA). But the key challenge is to maintain symmetry between dual networks, so as to obtain equal propagation delays and power consumption on differential signals. In this paper, we deal with the problem of timing unbalance. We study the impact of different placement...
This paper deals with the Design and Analysis of Floating point and Galois field multipliers using a pipelining technique called ??Wave pipelining??. Wave pipelining is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than conventional pipelining techniques. Wave pipelining can improve the throughput of a logic circuit while avoiding some of the overheads...
In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in wave dynamic differential logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing...
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated...
In this paper we present an architecture for nanowire layer in FPNI which is include switch boxes concept. The FPNI improves the Field-Programmable Gate Array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches which decreases both the area and power consumption of the circuit...
Interconnections play a crucial role in todays deep sub-micron designs because they dominate the delay, power and area. This is especially critical for modern million-gates FPGAs, where as much as 90% of chip area is devoted to interconnections. Multiple-valued logic allows for the reduction of the required number of signals in the circuit, hence can serve as a means to effectively curtail the impact...
This paper presents a comparative study of field programmable gate array (FPGA) implementation of standard and truncated multipliers using very high speed integrated circuit hardware description language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction...
A technique based on electrical pulse injection for the analysis of SETs propagation within logic resources of Flash-based FPGAs is developed. Experimental results provide detailed characterization of basic gates and realistic routing and logic paths.
The goal of this paper is to investigate the simulation capabilities of modern FPGA post-layout simulator (ISE from Xilinx) compared to real life behavior. A simple ring counter has been used as a test circuit and the delays between the outputs have been evaluated.
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