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The paper presents the comparison performance in terms of error performance between two modulation techniques, the BPSK and QPSK modulation. Both modulations were implemented on the Spartan 3E Starter Kit board. In order to compare the error performance of the two modulation techniques, it is necessary to express the error performance in terms of the average energy per bit (Eb). A brief description...
This paper presents a new improved system for collision detection that can be used in guiding visually impaired people. The system is inspired by the LGMD (Lobula Giant Motion Detector) neuron found in the neural system of the locust, which can avoid collisions by using visual information. The original algorithm used for collision detection was improved using different median filters. The new algorithm...
The purpose of this paper is to provide the results of an improved FPGA-based Detector. The paper is based on an overview of the PSK (Phase Shift Keying) modulation and on a BPSK(Binary Phase Shift Keying) Detector. An improved design, all digital, of the BPSK Detector is implemented on a Nexys2 board. The newness of our detector is brought by the randomness of the LFSR (Linear Feedback Shift Register)...
The paper presents the simulation of a BPSK Modulator using Matlab/ Simulink environment and System Generator, a tool from Xilinx used for FPGA design as well as the implementation of the modulator on a Spartan 3E Starter Kit board. The modulator algorithm has been implemented on FPGA using the VHDL language on Xilinx ISE 12.3. The modulated signal obtained from simulations was compared with the signal...
This paper presents an overview of the PSK and QAM modulations, two digital modulation techniques. Based on recent development of software tools and FPGA circuits, the present paper improves a solution for implementing the PSK demodulation technique on a Virtex 5 board. The design of a BPSK detector, all digital, implemented on the FPGA is also considered.
The goal of this paper is to investigate the simulation capabilities of modern FPGA post-layout simulator (ISE from Xilinx) compared to real life behavior. A simple ring counter has been used as a test circuit and the delays between the outputs have been evaluated.
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