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In this study, an energy-efficient, configurable chip that can store and display phone numbers was designed. The chip is incorporated into an alert bracelet that can be used by people with cognitive dysfunction. The bracelet provides an uncomplicated, flexible, operationally safe, and cost-effective method for locating wandering and disoriented people.
A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We particularly focus on creating a VCLB layout that enables a standard cell like design. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic...
Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured...
Structured ASIC is a well-developed technology that enables a shorter design Turn-Around-Time (TAT) as well as less non-recurring-engineering (NRE) cost for very deep submicron designs. Since 2003, Faraday technology has developed its own structured ASIC solutions. Based on its own competitive technology architecture, Faraday has proposed platform-based SoC solutions and realized more than 100 customer...
In this paper, we investigate via-configurable logic block (VCLB) architectures of different granularities and logic styles for standard-cell like structured ASIC. VCLB granularity ranges from a few to tens of transistors. Logic styles include those realized using series-parallel transistors and look-up table. VCLBs are designed to enable a standard cell design style so that we can establish a structured...
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18 um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a...
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited capability of placing more double vias (called vial) between metal 1 and metal 2. Such a limitation is caused by the way we design the standard cells and can not be resolved by developing better tools. This paper presents a...
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