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A new concept of the structure design with an alignment between the maximum band-to-band tunneling rate and electric field has been proposed to enhance the performance of TFETs. It was found that the specific gate of TFET to form an obtuse shape can dramatically improve the on-current of TFET, with over 4 order improvement in comparison to planar ones. This complementary TFET (CTFET) was also demonstrated...
In this paper, we propose an advanced tunneling field-effect transistor (TFET) structure. The fabrication method of proposed TFET is designed. The characteristics of the proposed TFET are investigated by device simulation.
We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGe-channel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor...
To study the High-k dielectrics on alternate semiconductor materials for transistors a modeling platform has been developed which implements a faster 1D Schrodinger-Poisson along with trap models. A fitting algorithm is used for the extraction of trap profiles which fits the model capacitance/admittance to the measurements in the least square sense. The extraction is illustrated on a subnanometer...
High performance 20nm-node PCRAM cell switching was successfully realized with the remarkable Ion/Ioff characteristics employing low aspect ratio poly PN diode on metal. Nice Ion/Ioff ratio was obtained by modifying stack of diode adopted in-situ boron-doped poly SiGe and thermal optimization with spike RTA. Basically, boron has high solubility and activation rate in SiGe matrix. In-situ boron-doped...
This review focuses on material challenges associated with III-V co-integration with Si for future CMOS. There is a huge volume of literature on this topic as implementation of III-V monolithic integration with Si has been the holy grail for last four decades; targeting a wide range of applications including RF devices, LEDs, lasers, photo-detectors and the like. The key drivers have been the cost...
Quantum-confined Stark effect of Ge(Sn)/SiGe(Sn) quantum wells (QWs) is analyzed by many-body theory. Calculated absorption spectra of Ge/SiGe-QWs are in good agreement with the experiment. Also, the effect of Sn-incorporation is investigated for mid-infrared applications.
Silicon photonics devices based on Ge/SiGe structures are promising. However their integration with silicon on insulator waveguides is a challenging point. We present an innovative approach to monolithically integrate low-voltage, broadband photonic interconnection on silicon.
We demonstrate polarization insensitive FWM-based wavelength conversion of 40Gb/s DPSK signals in a SiGe waveguide, with 0.42-dB polarization-dependent loss. A 1.5-dB Dower nenaltv was measured at a BER of 10−9.
We demonstrate strained SiGe-based carrier-injection MZ optical modulator with low driving current of 1.47 mA owing to the enhanced plasma dispersion effect in SiGe. The 10 Gbps modulation with clear eye opening is also obtained.
We have achieved the first monolithically integrated triple-junction InGaP/GaAsP/SiGe solar cell on Si substrate, achieving an adjusted efficiency of 20% AM0 1-sun. The practical achievable maximum AM0 efficiency for the optimal cell near this lattice constant is 39%. The combination of this high efficiency with the ability to process such cells on larger area lower-cost silicon substrates motivates...
Lattice matched and current matched GaAsP/SiGe tandem solar cell on Si has the potential of 40% efficiency. This paper describes our design, fabrication and improvement of this tandem solar cell. This tandem device has achieved efficiencies of 20.6% and 20.2% under 1X and 2.2X, respectively. Current matching between top cell and bottom cell is realized by manipulating the bottom cell active area and...
In this work, the potential of Si1−xGex Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of external resistance is observed for Si1−xGex Quantum Well...
In this study, different S/D contacting options for lateral NWFET devices are benchmarked at 7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-lattice results in 13% performance improvement. Also, we conclude that the integration of internal spacers between the NWs is a must...
We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high...
Strain feld distribution at the surface of SiGe nanomounds formed by heteroepitaxy is exploited to obtain a positional ordering of the closely spaced Ge quantum dots (quantum dot molecules). We demonstrated, that a low density of the lateral quantum dot molecules (up to 107 cm−2) can be achieved by tuning of the growth conditions. We present a growth model that provide physical insights into possible...
The tunnel field-effect-transistor (TFET), which is expected to achieve a subthreshold swing (SS) of less than 60mV/dec, is one of the most promising device concepts for enabling supply power scaling to below 0.5 V. Encouraging experimental heterojunction-TFETs results with MOSFET-like ON-currents have been reported recently [1]–[2]. However, the SS increased in both high and low drain current regimes,...
We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D2) anneal, which is ascribed to a 2x reduction in interface trap density (DIT). Furthermore, it is found that (1) TMAH treatment of SiGe prior...
We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
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