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A detailed statistical characterization of drain current local and global variability in sub 15nm gate length Si/SiGe Trigate NW pMOSFETs is carried out. An analytical mismatch model is used to extract the main matching parameters. Our results indicate that, despite their very aggressive dimensions, such devices maintain relatively good variability performance.
Coupled effects of substrate orientation and germanium concentration during silicon-germanium Solid Phase Epitaxial Regrowth (SPER) is analyzed through lattice kinetic Monte Carlo simulations. Atomistic events depending on the bonding environment allow to replicate the effects of alloying on SPER velocity of (100) substrates. The model is then used to draw predictions of the regrowth anisotropy in...
We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows...
The evolution of silicon and silicon-germanium pnp transistors is reviewed in this paper. The motivation for SiGe-pnp transistors in Complementary Bipolar (CBi) and CBiCMOS is discussed with a view on device parametric parameters that help gage the usefulness of these devices in analog and RF design. We review the basic process architectures and process building blocks for CBiCMOS. SiGe-pnp versus...
The performance of p-type silicon nanowire FETs with three different silicon-germanium cladding options is bench-marked against the silicon reference device. Low-field mobilities and full device characteristics are obtained from the solution of the subband Boltzmann transport equation, including phonon and surface roughness scattering. The subband dispersion is calculated using 6kp band structure...
A SiGe-on-SOI carrier-depletion Mach-Zehnder modulator is presented. Compared with Si modulators, it eliminates advanced lithography by enabling a dual-waveguide design using small SiGe waveguides for modulators and large Si waveguides for edge coupling. DC and high speed test results are included.
The terahertz technique has been a hot research topic in recent years owing to its unique characteristics for potential applications such as high resolution spectrometers and high data rate space communications. Rapidly growing research activities from worldwide researchers have been involved in developing terahertz components. This paper reports some typical achievements of developing terahertz components...
A 4×4 power amplifier (PA) array with end-fire on chip antennas is presented in this paper. In the PA array module, four-chips are stacked vertically and spaced by the metal holders. In a single chip, four PA blocks with a 1×4 end-fire on-chip antenna are integrated. 0.13-µm SiGe BiCMOS process is used for fabrication with the experimental ƒT and ƒMAX of 210 and 260 GHz, respectively. The 4×4-PA-array...
A SiGe-on-SOI carrier-depletion Mach-Zehnder modulator is presented. Compared with Si modulators, it enables a dual-waveguide design using small SiGe waveguides for modulators and large Si waveguides for edge coupling thus eliminates advanced lithography for inverse tapers. DC and high speed test results are included.
Selecting the material used as the device channel which connects the source to drain region is vital as it will affect the conductivity of the transistor. Recently, germanium was actively used as the diffusion material for source/drain and channel properties mainly for ρ type FinFET, however rarely in η type FinFET. This paper investigates the device performance of 7nm nFinFET for their various types...
Here we present an initial demonstration of a dual junction step-cell using single junction (SJ) GaAs0.76P0.24 cell, grown on Si1−yGey/Si substrates, as the top cell and Si as the bottom cell. To demonstrate step-cell, two SJ cells are connected in series, without removing SiGe/Si carrier from III-V cell, and illuminated Si cell area is varied. Measured efficiency of optimized demo step-cell under...
Tandem solar cells made from III-V layers grown on silicon have the potential for high efficiencies at relatively low cost. Recent work has produced a GaAsP/SiGe tandem with over 20% efficiency based on indoor measurements. In this work, improvements are made to this device and outdoor performance is reported for the first time. Light trapping and substrate thinning techniques developed on a SiGe...
We have investigated CMOS photonics based on heterogeneous integration of SiGe/Ge and III–V semiconductors on Si, which gives us opportunities to enhance functionalities of Si photonics through their superior material properties for electronic-photonics integrated circuits.
Emergency management (EM) is strongly dependent from an information system sufficiently flexible and appropriate to the operational characteristics and demands represent, according to the literature, one of the biggest challenges in the EM. The study presents the results of the identification of the Emergency Management Information System (EMIS) Critical Success Factors (CSF) in Mozambique. The 2013...
Thermal heat/phonon transport in single-crystalline Si and amorphous SiGe phononic crystal (PnC) nanos- tructures was investigated at room temperature. Thermal conductivities were compared between hexagonal-lattice PnCs, which have staggered alignment of circular holes, and square-lattice PnCs. In microscale structures, where thermal transport is diffusive, no difference can be expected. However,...
Technology scaling has led to unprecedented level of integration with billions of high-speed nanotransistors on a single chip reducing the cost per function. On the device technology front, with continued scaling, device engineers have achieved new transistor breakthroughs and introduced innovations at a rapid pace followed by successful launch of commercially successful products such as high performance...
In the advanced nodes of 28nm and below, small defects too can have a significant impact on the final yield results of wafers. As the technology node advances it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. In this paper we evaluate the influence of various processing parameters on the extent of "Unwanted...
We describe the use of high resolution X-ray diffraction (HRXRD) for inline metrology of strain relaxed buffer (SRB) layers and epitaxial layers grown thereon. The use of SRBs as a virtual substrate is a promising candidate for advanced CMOS logic at the 7 nm technology node and presents some unique challenges to traditional HRXRD measurements. To overcome these challenges, reciprocal space maps (RSMs)...
An analysis on the degradation of DRAM performance caused by the NBTI degradation of p-MOSFET is first to be reported. To improve the NBTI immunity, three candidates are examined. First, minimizing Si-H bonds at Si/SiON interface through controlling the heat-budget at BEOL shows a promising result in NBTI lifetime, but it is not appropriate for DRAM process since it decreases the refresh time. Next,...
Contact engineering of Ge-rich source/drain is of critical importance for the development of advanced nano-scale CMOS technology nodes. Germanosilicide or Germanide contacts with low Schottky barrier height are highly desirable to achieve low contact resistance for a Ge-rich source/drain. However, practical integration of Ge-rich SiGe into devices is complicated by its unique physical and chemical...
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