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As a tool to localize defects, OBIRCH is widely used in solving the problem of FAB low yield issue. Choosing a proper voltage is critical for the effective working of OBIRCH. This paper proposes a method to analyze the critical voltage of OBIRCH used to the finger metal structure. Based on the measurement data including current and voltage, an empirical formula has been simulated to calculate Sigma...
This paper describes the use of Dynamic Digital Modulation (DDM) technique for the non-destructive estimation of defect depth in flip chip and stack die packages. The thermal responses of various devices with different defect depths are analyzed using the DDM technique and the thermal rise time data extracted from the thermal signal are used to interpret the defect depth which are validated with Physical...
Wafer Level Chip Scale Packaging (WLCSP) involves more bumping process steps after receiving the passivated product wafer from the foundry manufacturing line. As wafer sort is usually tested after the bumping process, on the solder bump, any process drift during bumping, especially the contact resistance degradation at the Aluminum (Al) pad to Redistribution Layer (RDL) interface or RDL to solder...
Dynamic Fault Isolation is a very important step in the Failure Analysis process flow of VLSI circuits over the last decade. Key factors in successful dynamic FI include understanding the test methodology, knowledge of the design for test (DFT) features such as BIST and SCAN, and in interpretation of the fault isolation signals. The invited talk will also discuss a few recent advances that help with...
Driven by the next generation of electronic devices that require progressive miniaturization, stacked die packages have been developed to provide greater functionality in smaller package footprints. This provides a substantial improvement in the electrical performance while enabling continuous extension of the Moore's Law. Nevertheless, high circuit density and high complexity of interconnections...
Through the investigation of sleep mode IDDQ failure encounter in fabrication of a 28nm mobile application IC, this paper will demonstrate the Failure analysis techniques applicable for leakage source detection involving activation of power management feature rather than pure DC bias, we will also discuss the potential process/design weak point and proposed solution in deep submicron technology node.
Failure Analysis (FA) consists of fault verification, isolation, defect tracing, characterization and physical analysis. Flash memory is widely used in data storage. High density cell array makes flash memory prone to defects. In this paper, a NOR flash page failure case was studied. The failed page, consisting of 8 word lines and 512 bytes, cannot be erased. Light emission could help isolate the...
The experimental RTN-trap profiling method bas been demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. The...
The endurance and charge loss are the most critical issue in the design of a SONOS memory cell. The origin of the window closure and charge loss was partly caused by the electrons and holes mismatch along the channel lateral direction during the cycling. In this paper, two measurement techniques to observe the mismatch of programmed electrons and erased holes have been developed. It was demonstrated...
A methodology for simulating the device performance degradation considering the coupling effect of NBTI and SHE in SOI p-MOSFETs is proposed. NBTI models and thermal network are implanted into HiSIM with instantaneous parameter update during the transient simulation. The simulation results show that decoupling simulation will lead to non-ignorable inaccuracy.
The number of WLCSP (Wafer Level Packages) used in semiconductor packaging has experienced significant growth since its introduction in 1998. The growth has been driven primarily by mobile consumer products because of the small form factor and high performance enabled in the package design. And it is also attractive to WE (wearable electronics) and IoT (Internet of Things) products. Although WLCSP...
Combinational logic analysis has been introduced to improve fault isolation when using laser voltage probing on standard cells. The technique has been shown to offer more reliable isolation within a shorter time thereby increasing FI efficiency. This paper uses interesting case studies to showcase how incorporating into conventional laser voltage probing significantly improves the success rate of...
It has always been a challenge to identify the failure mechanism of electrical overstress and latch-up failures due to misleading failure modes observed from electrical fault isolation. A Latch-up failure event involving an I/O cell of a SoC device is investigated. The root cause is determined by combining failure analysis, layout and commonality studies. It is found that the presence of abutting...
As the semiconductor technology continues to scale, the stability and performance of embedded SRAM are growing concerns during the design and analysis stages. Maintaining an acceptable Static Noise Margin (SNM) in the embedded SRAM while scaling the minimum feature size and supply voltage of the integrated circuit (IC) becomes increasingly challenging. As a result, the manufacturing process window...
With rapid developments in semiconductor manufacturing technologies, new and more complicated challenges emerge in the Failure Analysis space. The real challenge arises when similar electrical data is obtained from transistor nano-probing from completely different defect types. Accurate data interpretation is therefore the key to unraveling and understanding the root causes of failure. This paper...
The failure analysis from the manufacturer could not fully explain the Cu-Al bond open and drift issues in some plastic encapsulated microcircuits. For further investigation, an insight analysis containing chemical deprocessing, cross-sectioning and mechanical opening was performed to define the root cause. Several new findings were observed to support a reasonable cause. The corrosion reaction of...
Electrostatic Discharge (ESD) and Electrical Overstress (EOS) continue to impact semiconductor components and systems as technologies scale from micro-to nano-electronics. This paper focuses on the state of the art of electrostatic discharge (ESD) and electrical overstress (EOS), with an emphasis on failure mechanisms and testing. The tutorial provides a clear picture of EOS phenomena, ESD and EOS...
GaN-based transistors are emerging as almost ideal devices for application in the power conversion field; however, several factors still limit their performance and reliability. This paper reviews the most common field-dependent degradation mechanisms in GaN-based power transistors. Based on the analysis of commercially-available devices we present data on: (i) the recoverable increase in on-resistance...
An improved method of a planar IC sample delayering by FIB is proposed. The sample cleaving and FIB milling from two directions increases the quality of the delayered area. SEM allows accurate endpointing of the delayering on the layer of interest. The method allows to increase the delayered sample area significantly.
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