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The quest for the universal memory has been pursued since several years, but as far results from scientific literature do not declare one single technology able to fit all the requirements of the memory hierarchy. Flash and DRAM cover more than 95% of the global sales in the semiconductor memory market [1], but none of the two is able to substitute the other. This appears to be true also for disruptive...
Industry-standard Circuit Reliability simulation Tools (ICRT) to simulate Channel Hot Carrier (CHC) is either not possible at the full-chip level consisting of few million transistors or time consuming and prone to abrupt termination of simulation due to resource usage anomalies at reasonable large sub-block level. We have proposed a hierarchical design-in-reliability methodology to identify CHC aging...
The performance of NAND flash based solid-state drives (SSDs) is highly dependent on the application's read and write characteristics [3], where "intensity" is defined as ratio of read:write requests, and "write- hot/cold" considers the write frequency. Moreover, NAND flash memory's reliability degrades with write/erase (W/E) cycling. To optimize performance and reliability, conventional...
Carbon-based nonvolatile resistive memories are an emerging technology. Switching endurance remains a challenge in carbon memories based on tetrahedral amorphous carbon (ta-C). One way to counter this is by oxygenation to increase the repeatability of reversible switching. Here, we overview the current status of carbon memories. We then present a comparative study of oxygen-free and oxygenated carbon-based...
An elementary step of trap and detrap processes of electron in the tunnel oxide during program/erase in NAND Flash memory is precisely studied. Owing to the high electric field during program and erase (P/E), the electron trapping and detrapping occur at the same time. Consequently, the detrapping process only leaves electrons in the deeper trap energy state (Etrap) than 3.5 eV. In addition, as-grown...
We propose a comparative analysis for Ge2Sb2Te5 (GST) and Ge-rich GST based Phase-Change Memory (PCM) devices in terms of program/read disturbs robustness. We present the characterization of the intrinsic drift of the materials, the investigation of the devices response to electrical stress and, finally, the study of the PCM cell behavior in extreme disturb conditions. A higher immunity for Ge-rich...
We developed a simple structure that can enhance the local electric field thus reduce the forming and SET/RESET operation voltage for WOx ReRAM. Si-doped W film is used to further increase the initial resistance and improve the reliability properties. TCAD simulation shows that the field enhanced structure provides an equivalent electrical field that would only be achieved by very small conventional...
Highly reliable LDPC ECC is introduced to improve the reliability of solid-state drives (SSDs). Although conventional AEP-LDPC ECC [3] is 12x highly reliable than BCH ECC, its error-correction capability is degraded due to the burst-errors and inaccurate log- likelihood ratio (LLR). To improve the reliability of TLC NAND flash, this paper proposes the burst-error masking (BEM) and program-disturb...
Conductive-bridge RAM (CBRAM) memory cells offer speed, voltage, and energy advantages over floating gate flash cells. Here, we describe a memory design which carries these cell-level advantages up to the product level, achieving 100x lower read and write power and 10x lower standby power than typical flash-based designs.
In this paper the memory performances of the TiN/HfO2/Ti/TiN and TiN/Ta2O5/TaOx/TiN memory stacks are compared. First, the bipolar switching parameters and the effect of the compliance current on the memory window and endurance are investigated. Then, the endurance and data retention properties are compared at a given operating current (100µA). Ta2O5 based memory stack exhibits a better memory window...
To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical- mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically...
The effect of read disturb on partially programmed blocks of MLC NAND is evaluated using experimental data from 2y-, 1y- and 1x-nm Flash memory devices. We demonstrate that when a partially programmed block is exposed to a large number of reads before it is finalized in terms of page programming, the remaining pages will exhibit a significant bit error-rate (BER) increase. The page-BER is characterized...
The resistive switching behavior in different HfO2/TiO2 nano crossbar structures of 100 x 100 nm² size is analyzed by means of DC voltage sweeps. The devices fabricated from 3 nm thin ALD layers of HfO2 and TiO2 sandwiched between Pt and Hf or Ti electrodes show VCM-type bipolar resistive switching after electroforming. For increased compliance current (cc) during set from 50 µA to 800 µA, the set...
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