The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We demonstrate high performance undoped Ge0.92Sn0.08 quantum well (QW) pMOSFETs with in situ Si2H6 passivation on (001), (011) and (111) orientations. (011) and (111)-oriented Ge0.92Sn0.08 QW pFETs achieve higher on-state current ION and effective hole mobility μeff compared to (001) devices. Ge0.92Sn0.08 (111) QW pFETs demonstrate a record high μeff of 845 cm2V−1s−1 for GeSn p-channel devices (Fig...
TSV (through-silicon-via) has been regarded as a key technology for 2.5D and 3D electronic packaging. However, the manufacturing of the through silicon interposer (TSI) is very challenging and costly. The minimization of the warpage of the TSV interposer wafer is crucial for successful subsequent processing, for example, thin wafer handling, backside via revealing and copper pillar bumping. In this...
Using model-based infrared reflectometry (MBIR) technique [1] we have developed a method for in-line process monitoring of polyimide passivation films to support the fabrication of fine pitch flip chip devices. A permanent passivation layer is incorporated in semiconductor wafers before the addition of solder in flip chip interconnects to protect sensitive on-chip components from chip-package interconnection...
In the development of emerging 3D IC packaging using TSV, wafer back side treatment is one of key processes. The TSV back side process called MEOL (Middle End Of Line) is a newly introduced process which is performed after front side treatment/bumping, or before chip stacking assembly. The MEOL process adapts some conventional fab processes such dry etch, PECVD, and CMP but there are some differences...
Interfacial delamination between backside of TSV thin wafer silicon, low temperature PECVD silicon nitride and UBM (under bump metallurgy) layer under room temperature and thermal cycling or processing have been investigated in this paper. FEA (Finite element analysis) was used to assessment the thermal stresses and the driving force of thin wafer bump UBM delamaination. The 3D modeling results were...
Packaging of optoelectronic devices becomes more and more challenging due to higher heat generation per unit volume. We experimentally investigated the packaging thermal resistance for a semiconductor laser device and compared results for two material alternatives for the electrical passivation layer. We used the time-resolved thermoreflectance technique to obtain the time response for the thermal...
In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent...
Organic/inorganic hybrid Schottky solar cells based on p-type conductive polymer poly(3,4-ethylenedioxythiophene): poly (sty renesulfonate) (PEDOT:PSS) in conjunction with n-type silicon substrates offer the merits of simple fabrication process and potential for lower cost. Here, we report an efficient organic/inorganic hybrid photovoltaic (PV) device based on silicon nanopillar arrays and PEDOT:PSS...
For the first time, a remote plasma chemical vapor deposition (RPCVD) based c-Si/a-Si heterojunction solar cell process was developed on thin crystalline silicon semiconductor-on-metal (SOM) substrate. In RPCVD systems, deposition temperature, deposition rate, and the distance of the sample from the plasma source can be varied to minimize the surface damage and enhance passivation quality. A silicon...
In this study, the feasibility of creating one dielectric layer system acting simultaneously as antireflection coating, phosphorous doping source, masking against metal plating, and surface passivation is presented. Moreover, a similar layer stack is described, which behaves as rear-side surface passivation, boron dopant source, and internal reflection mirror. The optical characteristics of these...
In this paper, we investigate the relationship between the deposition-process parameters of reactively sputtered aluminium oxide films and the passivation of silicon surfaces. A method of tuning the deposition process has been established that results in a reduced level of surface recombination, where surface recombination velocities as low as 8.5 cm/s have been achieved on 1 Ω·cm n-type monocrystalline...
We characterize heterojunction solar cells made from single-crystal silicon films grown heteroepitaxially using hot-wire chemical vapor deposition (HWCVD). Heteroepitaxy-induced dislocations limit the cell performance, providing a unique platform to study the device physics of thin crystal Si heterojunction solar cells. Hydrogen passivation of these dislocations enables an opencircuit voltage VOC...
This paper evaluates the effect switch design and control method have on the rise and fall time of a photoconductive microwave switch at 2GHz. The effects of switch dimensions, switch fabrication methods and light intensity of the control mechanism are investigated. Switch rise time is affected by switch dimension and optical illumination intensity. Switch fall time is dependent on passivation of...
The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain...
Surface passivation using Al2O3 deposited at 200 °C is examined to suppress surface recombination for carrier injection SiGe optical modulators. The modulation efficiency is improved by 1.3 by inserting Al2O3 layer prior to SiO2 deposition.
The effect of humidity on boron diffused and undiffused silicon samples passivated by aluminum oxide (Al2O3) synthesized by plasma-assisted atomic layer deposition (PA-ALD) has been investigated. We found that undiffused samples show a higher degradation rate than diffused samples. Under an ambient of 100% relative humidity and 50°C, the lifetime of an undiffused sample passivated by Al2O3 decreased...
This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly...
This paper presents a reliability study on a 15×15mm2 silicon interposer packages, 5 times larger surface than usual studies on wafer level chip scale package (WLCSP). Works were conducted in the frame of silicon platform developments for heterogeneous RF 3D modules, where the interconnections number is lower than in digital applications but the silicon interposer larger than conventional WLCSP. Several...
Recently, the demand on the 3-D integration using through-silicon vias (TSVs) and micro-bumps has been increasing for better electrical performance and smaller form factor. However, lots of doubtful concerns on the reliability of 3-D stacked chips still exist, which are Cu TSV expansion, transistor degradation or open failures on Cu contamination, micro-bump stress, and so on. In this study, we investigated...
This paper reports on the development of low temperature (<190°C) plasma-enhanced chemical vapour deposition (PECVD) processes used to deposit dielectric films for use as passivation layers over wafer back side revealed vias in thinned (<60μm), 300mm silicon wafers.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.