The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We have investigated finite element method (FEM) modeling of thermal stress analysis in a SiC power module using sintering Ag die-attach, and explored the reliability focusing on the initial cracking point caused by the thermal stress. The analysis results by FEM models support our experimental observations in the reliability tests of the fabricated modules, confirming that using direct-bonded-copper...
Despite many fatigue mechanisms published for Fan-out Wafer Level Package (FOWLP), most merely focused on stand-alone package reliability or solder joint capability. Only a few explored the failures of Chip to Board Interaction (CBI) due to the difficulty for perceiving the induced CBI failures. In this paper, a unique failure mechanism was first observed by an innovative test methodology in interconnects...
The monolithic integrated sensing chip is developed not only to fulfill but expand more territories of applications, including consuming electronic devices and automotive application. Therein, the thermal stress generated during packaging process is an inevitable concern for reliability of chip. This study focuses on the thermal stress generated during the die-attached stage for microelectromechanical...
We have analyzed 3D thermal stress profile under TCT using multi-physics solver for SiC power device heat dissipation structures with a direct chip bonding on Cu plate by Ag sintered layer. The results showed that the maximum stress value in SiC chip structure is higher than that in Si chip structure. This is because Young's modulus of SiC is higher than that of Si. The maximum stress point is at...
Cracks in die passivation adjacent to solder bumps due to thermal stress can lead to a multitude of failures including bond pad lifting. Modifying the solder reflow temperature-time profile is not trivial as this may impact the metallurgical properties of the solder ball. In this work, Under Bump Metalization (UBM) dimensions were optimized using finite element analysis (FEA) and response surface...
The metal layout design influences the reliability of the metallization in semiconductor products. An optimized design of the interconnect stack can help to reduce the incidence of dielectric and passivation cracking during Joule heating of the metallization in semiconductor back end of line (BEOL) structures. The elements of the metal stack have different material properties. Thermal stress from...
Environmental and electrical stress phases are commonly applied to automotive devices during manufacturing test. The combination of thermal and electrical stress is used to give rise to early life latent failures that can be naturally found in a population of devices by accelerating aging processes through Burn-In test phases. This paper provides a methodology to evaluate and compare the stress procedures...
Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DMA and CACHE interventions. The paper reports also...
This paper deals with the thermal, electrical and combined thermo-electrical ageing of some XLPE and EPR flat samples. The samples were aged for different ageing times and electric fields. Before and after ageing, the electrical properties (e.g. electrical conductivity and permittivity) were measured. The physical modifications of the specimens were analyzed, also. Combined stresses (electrical and...
A planar oxygen sensor with yttria stabilized zirconia (YSZ) based on high-temperature co-fired ceramic (HTCC) technology is presented in this paper. To protect the electrode from the exhaust gas, a porous layer is printed on the surface of the outer electrode. Also, an inner electrode is in contact with air reference atmosphere. Moreover, a heating element with a dissipative resistance is embedded...
Stress is a response to time pressure or negative environmental conditions. If its stimulus iterates or stays for a long time, it affects health conditions. Thus, stress recognition is an important issue. Traditional systems for this purpose are mostly contact-based, i.e., they require a sensor to be in touch with the body which is not always practical. Contact-free monitoring of the stress by a camera...
For the high-temperature structure, there exists correlation between the thermal stress and thermal intensity in most cases because of the two-sided effects of temperature. This paper proposes a time-varying response surface method considering correlation between the structural response value and structural response threshold based on Copula models. Firstly, the time-varying model of structural response...
Partial shading effect is one of the serious problems that affect BIPV systems; it leads to significant reduction in electricity production. Under these adverse conditions, shaded cells will dissipate energy in the form of heat rather than producing it. If it persists, this heat dissipation may cause an irreversible damage to the PV module. In this work, the electrical and the thermal behaviors of...
Physically meaningful and easy-to-use analytical predictive stress models are developed for a through-silicon-via (TSV) design using theory-of-elasticity based approach. Two extreme cases of the TSV height-to-diameter ratios are considered: disc-like vias, with the aspect ratios below 0.25 (plane stress approximation can be employed in this case), and rod-like-vias, with aspect ratios, above 2.5 (plane...
A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal-oxide-semiconductor field-effect...
Fan-out wafer level package (FOWLP) technology becomes more attractive because of its flexibility for integration of diverse devices in a very small form factor. As FOWLP is composed of various materials, the proper structural and material selection designs are important to meet reliability requirements. In this study, thermal properties of FOWLP with different package structures were evaluated to...
For 3D-LSI devices using the through silicon via (TSV) process, there are many reliability issues regarding the large thermal-mechanical stress and deformation volume changes caused by mismatch of the thermal expansion coefficients (CTEs) between the Cu and Si substrate in the device active area. In this paper, we investigated the TSV leakage current in metal-insulator-semiconductors and studies MOSFET...
The rising number of photovoltaic (PV) units in distribution grids will necessitate significant investments in grid reinforcements. The industry-standard in grid planning is to use the rated power of the PV systems to estimate grid stress. However, in this paper, we show based on an empirical analysis of real-world data that the maximum feed-in of PV units is lower than their rated power. Consequently,...
This paper reports a method of measuring the on-chip thermal stress for silicon resonant accelerometer (SRA). This method could be used to evaluate the stress-temperature characteristic of SRA, and that would help to focus the problems exist in SRA. Clamp-clamp Double Ended Turning Fork resonator is used as a basic measurement unit. Analysis of the accuracy and noise in stress measurement is given...
In this work, the 14 nm CPI (Chip and Package Interaction) challenges, development and qualification were investigated by using 80 um pitch Cu pillar BOL (Bump on Lead) technology in flip chip CSP package. We evaluated 14 nm BEOL (Backend of Line) film strength and adhesion in the torture tests as an early assessment. After passing the torture tests, the package is evaluated in the CPI reliability...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.