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Previous works on detecting and locating manufacturing faults-shorts, stuck-at, and open on an inters witch link of a channel in a network-on-chip (NoC) have been based on the assumption that these faults do not coexist. The works failed to diagnose all these faults when this assumption is relaxed. A deficiency for non-diagnosability of these faults is then represented. A packet address driven test...
6T SRAM bitcells for high density 64MB SRAM has been designed. Test chip with memory arrays based on these bitcells was manufactured and characterized for radiation effects. The device is SEL immune, has an error rate less than 4∙E-18 errors/bit•day.
In this paper a method is presented to address the automatic testing of analog ICs. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automaticaly by a proposed optimization algorithm. Adopting a defect-oriented...
NP-complexity of tasks of the test analysis for the developing computer systems led to emergence of new methods of generation of the tests in particular using evolutionary models. The operations of a mutation, a krossingover applied in them, fitness functions depending on object of the analysis gain special properties, mechanisms of action and dependence on evolution environment. In the real work...
this paper presents SEE test results of 256k RAM with preliminary γ-ray irradiation and comparison with previous not irradiated samples tests. Difference between irradiated and not irradiated samples test results for SEL is shown.
Transformer condition monitoring and assessment is crucial as it can be applied to evaluate its maintenance needs. The current trend is to leave critical power transformers in service uninterrupted unless the monitored parameters indicate otherwise. This ensures optimal use of the facility and uninterrupted power supply to consumers. This paper presents the evaluation of the health status of a transformer...
Silicon interposer based 2.5D IC is a promising solution for providing low interconnect delay, high bandwidth, and heterogeneous integration. It has been considered as an alternative of the 3D technology. However, testing is a big issue in 2.5D IC. This paper presents a new contactless testing mechanism for pre-bond interposer testing. Our testing mechanism attempts to detect a defective interposer...
A utility usually installed modern power system protection relays from multiple manufacturers and models. The testing of the relays is very challenging due to its complexity. This would increase expenses due to additional test duration and longer disturbance of power for the substation can't be energized. Therefore a test that could be done without prior accessing the setting would be needed for faster...
We propose a parallel training framework of convolutional neural networks (CNNs) for small sample learning. In the framework we model the feature filter process and show Sadowsky energy distribution exists in the model. Using Sadowsky energy distribution, the weights in convolutional kernels can be rearranged after each update according to special cases. With this rearrangement, each CNNs in the framework...
We present the results of single event effects (SEE) testing and analysis investigating the effects of radiation on electronics. This paper is a summary of test results.
Long test application time is an important problem in system-on-a-chip (SOC) design, and test scheduling is the main way to solve this problem. It is equivalent to the NP-complete 2-D bin-packing problem, each core test is represented by a rectangle with height equal to the TAM width and width equal to the test time. In this paper, we present a time-divided of IP test to solve SOC test scheduling...
Among many challenges in the development of 3D-IC products, cost is one of the top concerns. Within cost elements, known-good-die (KGD) and 3D-IC integration yield, are among a few biggest impacting factors. In order to achieve high 3D-IC integration yield, build-in self-repairing, design-for-testing (DFT), diagnostic, and failure analysis (FA) capabilities, are very important elements of 3D-IC FPGA...
Adding functionality to a passive Si interposer used in 2.5/3D integration, can result in system cost reductions. In this work, active components (diodes, BJT, …) have been integrated on Si interposer using a new low-mask process flow. This low-cost process enables: (1) to move part of the area hungry ESD protection from the stacked dies to the interposer; (2) the realization of pre-bond testable...
Most works related to convolutional neural networks (CNN) use the traditional CNN framework which extracts features in only one scale. We propose multi-scale convolutional neural networks (MSCNN) which can not only extract multi-scale features but also solve the issues of the previous methods which use CNN to extract multi-scale features. With the assumption of label-inheritable (LI) property, we...
Adding functionality to a passive Si interposer used in 2.5/3D integration, can result in system cost reductions. In this work, active components (diodes, BJT, …) have been integrated on Si interposer using a new low-mask process flow. This low-cost process enables: (1) to move part of the area hungry ESD protection from the stacked dies to the interposer; (2) the realization of pre-bond testable...
In this work, we demonstrated a simple method to test the point contact design and determine the Surface Recombination Velocity (SRV) of the point contact solar cells from a single PL image. The thermally grown silicon dioxide is patterned by using lithographic means. The size, pitch and pattern of the point contact opening holes are varied in order to find the relationship between opening density...
High-efficiency tunnel oxide junction cells are based on the Metal-Insulator-Semiconductor concept, which combines a tunnel oxide junction with doped a-Si thin film emitter layers on n-type CZ silicon wafers. The cells are bifacial by design and allow for almost equal power generation from the front and from the back. Packaged inside a module with transparent front and backside allows for light capture...
Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its silicon area cost makes it unattractive for widespread use. In this work, we reuse the Razor topology in order to achieve low power scan testing operations and make this technique a viable solution which will serve both on-line and off-line testing...
Monkey Fuzz Testing (MFT), a form of random testing, continues to gain popularity to test Android apps because of its ease of use. (Untrained) programmers use MFT tools to fully automatically detect certain classes of faults in apps. A challenge for these tools is the lack of a stopping criterion -- programmers currently typically stop these tools when they run out of time. In this paper, we use the...
Testing of Analogue/Mixed Signal ICs has reached a transition point. In the past AMS testing was based on functional tests that ensured that the analogue specifications were met. Unfortunately this approach is expensive; testing an ‘analogue’ transistor can be 1000x more expensive than testing a digital transistor. What is even a bigger concern in industry is that a large fraction of the AMS test...
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