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Combination with the RRAM analytic model with varation and the Monte Carlo simulator based on the microcosmic processes of oxygen vacancies and oxygen ion's generation, transportation and recombination, a TMO RRAM reliability simulation platform is developed to simulate and evaluate the main reliability issues of RRAM including retention, endurance, operation disturb considering the intrinsic variation.
Glass interposer is introduced as an alternative to silicon interposer for 3D integration due to the attractive advantages such as excellent electrical isolation, extremely low insertion loss, adjustable coefficient of thermal expansion (CTE), and most importantly low cost potential with the capability of large panel size fabrication. In this study, a novel scheme is proposed to fabricate glass interposer...
A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively...
We proposed a new statistical evaluation method to justify the microstructure evolution process of conductive filament (CF) in the reset operation of resistive switching memory (RRAM) according to the dependence of the Weibull slope of reset parameters on the CF size. We demonstrated that in Cu/HfO2/Pt device the CF can be controlled to be ruptured abruptly, which is more advantageous to the reliable...
This paper describes the use of Differential Cone-Beam algorithm to improve CT reconstruction resolution for enhanced visualization of semiconductor flip chip package defects. Results demonstrated improvements in CT reconstruction resolution and time.
Field failure modes are studied for VCSELs in high volume optical mouse applications in non-hermetic conditions. A new signature of catastrophic optical damage (COD) was reproduced by using temperature humidity tests without a ramp. Such conditions cause oxidation for a VCSEL type with a Gallium Arsenide cap layer. The robustness against environmental influences can be improved by adding a Silicon...
N-type InGaAs MOSFETs with self-aligned nickel-InGaAs alloy and ex-situ ALD Al2O3 as gate dielectrics was successfully fabricated. The InGaAs MOSFETs exhibit an S/D resistance (Rsd) that is lower than that in P-N junction devices due to the low Schottky barrier height and the peak mobility was about 1138 cm2/V-s and the interface state density (Dit) was about 1012 cm−2eV−1 at Et = Ev + 0.6 eV by using...
The abnormal turnaround phenomenon of threshold voltage for the p-type low temperature poly-silicon thin film transistors (LTPS TFTs) stressed under a specific negative DC bias condition, which the gate voltage is about one half of the drain voltage, is investigated. There are two turnaround points for the TFT stressed with prolonged time. The sampling current of the TFT under the biasing stress is...
In this study, we analyzed the In2O3 thin films with different oxygen flow rate during sputtering as the transistor's channel layer. The electrical analysis including device's reliability and material analysis were both examined.
Generally, LCD(liquid crystal display) driver IC(integrated circuit) requires high voltage of more than 10V and adopts MTI(middle trench isolation) scheme which is deeply trenched to get isolation characteristics on the high voltage according to chip shrinkage. The Vth(Threshold Voltage) shift of HV devices after HTOL(high temperature operating life time) becomes much more serious hazard for product...
The accuracy of ion implantation is very important in semiconductor manufacturing and will directly affect the performance of the individual devices and even the whole chip. The deviation of IMP energy, dose and angle are often encountered because of the abnormality of implant equipment or process design limit. The ion implantation energy, dose and angle information can be qualitatively and quantitatively...
With the fast development of semiconductor fabrication, IC devices reduce their feature size and increase their complexity continuously. Failure analysis (FA) for such devices needs advanced and powerful tools. Here, we introduce two advanced FA technologies: Thermal emission microscopy (THEMOS) and 3D X-ray microscopy. Several industrial cases using these two technologies to identify failures were...
In this paper, a thorough investigation on a memory yield detractor due to metal void is presented. The metal void was found to have a strong dependency on isolated well size. It was formed due to galvanic effect. The failure mechanism in this unique case was found due to a potential developed from charges on the wafer surface and opposing charges trapped in the well. The post-etch solvent acted as...
We report investigation about three types of conductive carbon particles viz. pure carbon particles, SiO2 filler mixed carbon particles, and SiO2@C core-shell particles in epoxy encapsulations of IC. SEM, EDX, FIB voltage contrast imaging, and Raman spectroscopy are used to characterize conductive carbon particles, and to identify their potential origin.
In the paper, we develop and implement the processes of tape on-off and Ag mirror-reaction to the previously developed size scalable inkjet printing process technique, i.e. CPLoP (Combined Process of Lift-off and Printing) for continuing its future interconnect applications in flexible microelectronics. The newly developed processes not only reduce coffee ring effect but also improve better electrical...
This paper elucidates the importance of ion-yield enhancement through primary-ion bombardment in ultra-high surface sensitive Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS) measurements of Aluminum bond pad fluorine contamination. A good correlation is achieved, R2 of 0.97, with Auger Electron Spectroscopy (AES) that is commonly used for bond pad surface contamination quantification.
Wafer level system integration (WLSI) as the new system scaling technology platform is taking the stage in parallel to transistor level Moor's Law scaling to drive the semiconductor industry moving forward in new mobile computing and Internet-of-Thing (IoT) markets. Two key WLSI technology platforms, Chip-on-Wafer-on-Substrate (CoWoS) and Integrated Fan-Out (InFO) are introduced and their merits are...
The rapid pace of technological progress over the past 40 years would not have been possible without a concomitant improvement in long — term reliability of circuits [1]. Despite significant challenges, circuit reliability has been maintained, preventing it from constraining the rate of scaling. Looking forward, we anticipate almost continual innovation in the architecture and materials of transistors...
1320 nm Continuous Wave (CW) laser is conventionally used for Timing Analysis techniques like Laser voltage probing which has spatial resolution limitation as the technology node scales down. This paper illustrates case studies using 1064 nm CW laser for timing analysis and highlights its spatial resolution advantages for use in Fault Isolation.
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