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In this paper, a novel 3D stacked package structure with horizontal fins is designed to solve the heat dissipation issue. In order to verify the thermal performance, a 3D stacked package test vehicle with five chips and two interposers is built in a CFD software-Icepak. The size of the chip is in accordance with commercial thermal test chip (TTC-1002, TEA). Three different cooling methods of this...
It is well known that Joule heat losses in integrated circuits (ICs) may change electrical behaviors of devices, especially semiconductor components. In this paper, a meshless approach based on a radial point interpolation method (RPIM) is developed to numerically model the coupled electrical-thermal process in time domain. The effectiveness of the proposed RPIM is verified through simulation of thin-film...
An efficient transient thermal simulation of 2.5-D integrated system with through silicon via (TSV) interposer is presented by the equivalent thermal model and the alternating-direction-implicit (ADI) method. The equivalent thermal conductivities of TSV interposer and bump layers are extracted properly. The temperature-dependence of thermal conductivity is taking into account in the modeling as well...
In this paper, the CNT TSVs, as well as Cu/CNT composite TSVs, are investigated based on the equivalent circuit model. The effective complex conductivity, which incorporates the kinetic inductive effect of CNTs, has been employed for high-frequency characterization. The performance comparison between Cu, CNT, and Cu/CNT composite TSVs are carried out. It is found that Cu/CNT composite TSVs can be...
A band-pass-filter (BPF) based on silicon substrate was designed and simulated. Different software was applied to design and simulate the character of the filter. A three-order filter was designed dedicating to range 2.4 GHz-2.5 GHz use. The ideal topology circuit was designed with passive inductors and capacitors. Moreover, the integrated passive devices (IPDs) were modeled and simulated with thin...
A band-pass-filter (BPF) based on silicon substrate was designed and simulated. Different software was applied to design and simulate the character of the filter. A three-order filter was designed dedicating to range 2.4 GHz-2.5 GHz use. The ideal topology circuit was designed with passive inductors and capacitors. Moreover, the integrated passive devices (IPDs) were modeled and simulated with thin...
CPW lines on a 0.015 0-cm resistivity silicon substrate are simulated using HFSS. The electric field distribution from HFSS is analyzed to demonstrate that silicon substrate loss plays an important role and cannot be ignored. A novel physics-based model is developed to predict the characteristics of the CPWs and compared with measured data. A good agreement is obtained up to 110 GHz and demonstrates...
In order to reduce the power consumption of modern electronics, the operating voltage needs to be significantly reduced. The electron hole bilayer tunneling field effect transistor (bilayer TFET) has the potential for reduced voltage operation. [1, 2] The device structure is shown in Fig. 1. Recent simulations of the bilayer TFET show poor on-state current [1] and electrostatic gate efficiency [2]...
The silicon industry has witnessed a half-century gallop of electronics. When technologies reached their limits, new technologies are budding out and prolong the unbreakable Moore's Law. This time, Through Silicon Via (TSV) is considered the most promising technology trend in the next decade. In this paper, we study the electrical characters of a TSV-bump combination under the ground-signal-ground...
We introduce an accurate and efficient method to extract high-frequency parallel admittance (capacitance and conductance) among multiple Through-Silicon-Vias (TSVs). Our method utilize the analytical expression of TSV's MOS capacitance and the 3D quasi-electrostatic (QES) scalar potential Green's function in layered media for extracting the inverse of complex capacitance matrix of TSV segments, with...
Three dimensional integrated circuits (3D ICs) have attracted much interest in the recent past, because of their capabilities for more efficient device integration and faster circuit operation. 3D integration relies on through silicon via (TSV) interconnection and interlayer bonding between the silicon layers. Because 3D IC is vertically stacked, higher temperature as well as temperature concentration...
Transmission characteristics of a coaxial through-silicon via (C-TSV) interconnect are studied according to our proposed lumped-element circuit model in this paper, with some numerical results given for their design as well as optimization. The influences of their geometrical and physical parameters involved on their transmission and reflection parameters are examined and compared in detail, such...
Through Silicon Vias (TSVs) are expected to play an increasingly important role in next-generation microelectronics packaging. Even when the challenge of attenuation is overcome, crosstalk remains a major concern in TSV design. In this paper, it is shown that, at frequencies above 20 GHz, near-end crosstalk can easily exceed -20 dB. Traditional analytical models for crosstalk are compared to full-wave...
A charge based compact model with self-heating effects has been developed for LDMOS transistors. Both the channel and drift regions in LDMOS are modeled without adding an internal drain node. An efficient scheme for including self-heating effects is implemented in the model, which requires no thermal network. A comparison with measured data from an LDMOS shows that the model has excellent accuracy...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
High density through silicon vias (TSV) can be used to build 3DICs that enable unique applications in computing, signal processing and memory intensive systems. This paper presents several case studies that are uniquely enhanced through 3D implementation, including a 3D CAM, an FFT processor, and a SAR processor. The CAD flow used to implement for these designs is described. 3DIC requires higher fidelity...
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
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