The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The following topics are dealt with: design; EDA concurrency; CAD for FPGA; analog performance modelling; manycore processors; formal verification; modern chip layout; application mapping; power efficiency; variation-aware design; multi-core simulation; mixed-signal power optimisation; nanodevices; dynamic verification; emerging biotechnologies; cache optimisation; embedded system modelling; ESL Hand-Off;...
New technology and innovative usage models are driving the industry towards the ubiquitous use of wireless communications. The result is an end-to-end re-examination of radio architecture from the front end module to the MAC and the expected shift from largely analog to nearly pure digital radio design. Even RF power amplifiers will be digital, rather than analog in nature. Most importantly, radios...
The global wireless landscape continues to change as demand for 3G technology accelerates. Qualcomm is meeting the challenge with its highly integrated SoC solutions that enable customers worldwide to bring more advanced consumer devices to market faster. Relationships and tight collaboration continue to play an integral role in product development, as it becomes more crucial than ever for partnering...
Today’s electronic devices are multi-faceted, software-intensive systems that interact with the real world. These interactions create a new kind of complexity that increases pressure on engineering teams to deliver the right product under shrinking schedules. These multi-disciplinary teams are inhibited by gaps between the different tools and workflows they must use for system concept development,...
Two consultants, each with over twenty years of experience designing integrated circuits at a variety of companies large and small, are fed up with the imperfect flows typically used by their clients. Drawing on a career's worth of mistakes knowledge, they present a set of coherent engineering principles for building a better flow infrastructure.
Modern microprocessors are becoming increasingly parallel devices, and GPUs are at the leading edge of this trend. Designing parallel algorithms for manycore chips like the GPU can present interesting challenges, particularly for computations on sparse data structures. One particularly common example is the collection of sparse matrix solvers and combinatorial graph algorithms that form the core of...
The computer industry has a problem. As Moore's law marches on, it will be exploited to double cores, not frequencies. But all those cores, growing to 8, 16 and beyond over the next several years, are of little value without parallel software. Where will this come from? With few exceptions, only graduate students and other strange people write parallel software. Even for numerically intensive applications,...
The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on parallel microprocessors. We believe that an ad hoc approach to parallelizing CAD applications will not lead to satisfactory results: neither in terms of return on engineering investment nor in terms of the computational efficiency...
This paper presents a novel logic synthesis method to reduce the area of XOR-based logic functions. The idea behind the synthesis method is to exploit linear dependency between logic sub- functions to create an implementation based on an XOR relationship with a lower area overhead. Experiments conducted on a set of 99 MCNC benchmark (25 XOR based, 74 non-XOR) circuits show that this approach provides...
We propose a new resynthesis algorithm for FPGA area reduction. In contrast to existing resynthesis techniques, which consider only single-output Boolean functions and the combinational portion of a circuit, we consider multi-output functions and retiming, and develop effective algorithms that incorporate recent improvements to SAT-based Boolean matching. Our experimental results show that with the...
In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test...
FPGA application developers often use pipelining, C-slowing and retiming to improve the performance of their designs. Unfortunately, registered netlists present a fundamentally different problem to CAD tools, potentially limiting the benefit of these techniques. In this paper we discuss some of the inherent issues pipelined netlists pose to existing timing-driven placement approaches. We then present...
The continuous technology scaling brings about high-dimensional performance variations that cannot be easily captured by the traditional response surface modeling. In this paper we propose a new statistical regression (STAR) technique that applies a novel strategy to address this high dimensionality issue. Unlike most traditional response surface modeling techniques that solve model coefficients from...
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topology generation. A new kind of GA is developed, where a fraction of the offsprings in each generation is built from building blocks or cells obtained from previous generations. The cells are stored in a hierarchically arranged...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.