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The semiconductor packaging technology trend for electronic products continues to achieve greater miniaturization and higher functionality. Thinner profile chip scale packaging (CSP), such as flip chip CSP (fcCSP), with increasing die complexities is a very important technology for next generation communication devices and internet of things (IoT) applications. Recently, integrated fan out wafer-level...
This paper reports on a large-size CPU package for UNIX servers which employs embedded thin film capacitor layers. The substrate of this package has two thin film capacitor layers in the surface of the core layer, which has a capacitance of 25 uF in total. In order to adopt this package substrate, we confirmed the effect of the thin film capacitor layers on the package assembly process. We actually...
With the rapid growth in the mobile industry, Package-on-Package (PoP) technology has been widely adopted for the 3D integration of logic and memory devices within mobile handsets and other portable multimedia products. The PoP solution offers significant advantages, including increased density through stacking logic and memory devices in the same formfactor and a high degree of flexibility for variable...
This work reports the reliability of Infineon's CoolGaNTM 600V Enhancement mode GaN-on-Si transistors under high temperature reverse bias operation. Using the most conservative lifetime model; the extracted lifetime at use conditions of 480V, 125°C at 0.01% failure rate is greater than 70 years. The extracted activation energy (Ea) is 0.77eV with a single failure mode, Drain to Substrate. A common...
The formation of a high temperature die attach based on transient liquid phase (TLP) bonding is demonstrated using the binary system Ag-Sn in a sputtered thin layer approach. The microstructure and shear strength are compared to a foil based approach and show the successful replacement of the Sn foil and thus a simplification of the stack assembly. The diffusion of the Ag-Sn system is investigated...
Packages of commercial Gallium-Nitride power semiconductors present increasingly small dimensions to enable low parasitic inductance, increasing the heat flux density of the package and the challenges associated with their thermal management. This paper compares between Printed Circuit Boards and Direct Copper Bonded as substrates for a Gallium Nitride based half-bridge from a thermal and reliability...
The plasma activation is a promised process to improve the bonding performance for materials pretreated with the plasma. In this study, the chips studded with gold bumps flipped-bonding onto alumina substrates using the thermal compressional bonding. To improve the bonding performance of gold bumps onto copper electrodes, both gold bumps and alumina substrates were pretreated to Ar/H2 plasma at 400...
In this study, a steady and comparatively smooth Ni-P coating on the surface of diamond/Al composite substrate was fabricated by electroless plating, which can outstandingly improve solderability of the composite. By controlling the deposition time, we obtained the growth curve of the Ni-P coating, and as a result we can adjust the thickness of the coating. The solderability was tested by soldering...
Plastic package of integrated circuit has the advantages of excellent performance, light weight, small size, and outstanding mechanical properties, which can be widely applied to weapons and equipments, aerospace, and other important areas. Due to the thermal mismatch of CTE, the traditional substrate-type plastic package is more likely to have a series of failures such as delamination and warping...
Recently, developing thick interfacial intermetallic compound layers with rough morphology has been detrimental to the long term solder joint reliability for lead free solders currently. A novel method has been developed to control the morphology and growth of intermetallic compound layers between pure Sn solder ball and Cu substrate by doping flux with amount of 2wt.% metallic Cu nanoparticles. And...
In this paper a kind of SSPC was designed and fabricated using thick film hybrid circuit technology. More than 1000 SSPC products went through the screening test according to GJB2438A. The screening procedure including thermal shock, high temperature power burn-in test, constant acceleration, hermetic sealing test and particle impact noise detection (PIND). Also 1000h life test was applied to samples...
The SnSbNi solder pastes were reflowed at 270°C and 280°C between the MvpLED chip and the AlN ceramic substrate, and then the SnSbNi solder joints were aged respectively at 200°C for 1h and at 250°C for 3h. The interfacial microstructure and constituents were investigated by SEM and EDS. After the reflow reactions, a thin layer of IMCs was formed at the chip/solder and solder/substrate interfaces,...
To study the thermal cycling reliability through the SMT technology, this paper based on the EAM experiment to test the correction of the ANSYS analysis. We have a deeper comprehend on the affluence of the creep property, to give a conclusion whether the SMT technology is reasonable. The results show: QFN solder is the main factor; In the thermal recycle analysis, the location in the edge of solder...
In the transition to lead-free process, one of the most prominent problems is the lead-free solder joint interconnection reliability. Interconnection failure analysis is an important tool for improving the lead-free PCBA product design as well as assembly process quality. Combining a typical fault case, this study deeply analyzed the failure phenomena and the failure mechanism as to interconnection...
In order to understand of the relation between the configuration of vertical via interconnection and its transition properties, the performance of millimeter wave wideband vertical via interconnection is investigated in multilayer LTCC substrate in this paper. From physics-based equivalent circuit modeling approach, the equivalent circuit are related to the geometry directly, which is an efficient...
Conductive anodic filament (CAF) formation, a failure mode in printed circuit boards (PCBs), which has been reported in 1976, has caused catastrophic field failures on electronic product. With the trend of high circuit density demands in organic packages, the pitch of plated through holes (PTHs) in packages should be reduced, and the amount of CAF failures is expected to be significantly higher. The...
Large scale and high density packaging of ASICs are usually achieved by FCBGA forms. The structure and materials are more complicated in FCBGA, which would cause reliability concerns in situations where thermo-mechanical stressing is dominant. Accelerated temperature cycling reliability test was performed on 90-nm/8-level copper based FCBGA packaging devices, and open failures dominated by thermo-mechanical...
This paper will discuss the fundamental study on nano-silver pastes newly developed with a unique approach using MO (Metallo-organic) technology. MO technology provides a low-temperature sintering capability. The nano-silver pastes show high electrical and thermal performance. However, degradation of die shear strength has been found by thermal cycling test due to the fragility of porous sintered...
Soft soldering is still the standard bonding method in order to provide a large void-free joining area in power electronics module applications. Ag sintering has been proven for small-area die attach applications to increase junction temperature and reliability. In this paper, we explore silver sintering technology further for large-area high-temperature substrate bonding in order to enable full benefits...
The key role that underfill materials play in highly reliable, advanced flip chip organic packages has generated an increased focus on their behavior and structure. One such behavior relates to the observation of filler separation from the resin matrix which, to date, has been predominantly attributed to gravity or capillary flow. The phenomenon of silica filler separation is discussed in the context...
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