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In this study, we perform a top gate field effect transistor by using the integration of novel materials such as graphene as active channel and fluorinated graphene as dielectrics on flexible Polyethylene terephthalate (PET) substrate. These device shows high carrier mobility (∼969 cm2/v.s) at a drain bias of +0.5V. It shows good mechanical flexibility and electrical stability after bending measurement...
In this paper, we present a study on protective coating techniques for thin film X-TEM sample preparation. The study shows that proper choice of the protective layer before FIB cross section is a crucial step to maintain the film profile and make sure the accuracy of the thickness measurement. Silicon native oxide is used as the target sample. We have investigated PECS metal sputtering followed by...
In this paper, we performed accelerated degradation testing (ADT) of a certain type of driver IC under different humidity stress levels. We keep the drivers in storage under same temperature but different humidity; measure the determined sensitive parameter of the driver with fixed time interval, then model the degradation path to obtain the pseudo-failure lifetime. Finally, we analyze the test data...
3-Dimentional (3D) X-ray imaging significantly increases the visibility of the bond wires and lead frame structures of the complicated integrated circuits (IC) packages, particularly for the less visible Copper (Cu) bond wires used in more recent IC devices. It has become a very useful and effective technique for detecting package related failures without going through the lengthy physical analysis...
In this paper, we present one simple die-level backside silicon thinning preparation approach to enable fault localization of vertical trench or highly doped silicon substrate power semiconductor devices. The methodologies are illustrated for understanding and immediate application at any lab environment. Effectiveness of the method is evaluated through qualitative judgement of image resolution clarity...
Due to the limitation of conventional FA technique, fault isolation of small magnitude IDDQ (Direct Drain Quiescent Current) is still a great challenge. Through a case study of a sleep mode IDDQ failure in a 28nm mobile application IC, by introduction of DRC tools, this paper presents an innovative isolation approach for detection of layout pattern related leakage weak points.
This paper describes the use of Lock-In Thermography (LIT) technique to determine the defect Z-depth in flip chip. An empirical phase shift versus applied lock-in frequency plot for Flip-chip is first created by using samples with known defect Z-depth. The actual experimental phase shift data from reject samples with unknown defect locations are then measured and compared against the empirical phase...
A back-side grinding CMOS-MEMS process is well established for thinning wafers down to tens of micrometres for use in stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in MEMS/CMOS wafers thinned down to 35∼275 μm by means of a micro-Raman technique. We found that the...
RF Power amplifier often demands Zero-defect in application. However, it sees non-uniform stress during application. The time depend stress level depends on the input signals. This paper presents a way to predict the gate oxide lifetime, not only for the intrinsic oxide breakdown, but also for the extrinsic oxide breakdown. An appropriate gate oxide screening condition would enable the desired quality...
This paper describes the electrostatic discharge (ESD) failure caused by parasitic BJT in N-substrate process. The study of ESD failures in P-substrate process[1-3] has been a topic of increasing interest. Meanwhile N-substrate process, which may cause unexpected ESD failure, has hitherto received little attention. Through data analysis, unexpected ESD failure in N-substrate process may be attributed...
An investigation of radiated reliability of HBT and MOSFET which fabricated on 0.35 μm SiGe BiCMOS technology is presented under dose rates of 500 mGy(Si)/s and 1 mGy(Si)/s with a 60Co γ irradiation source. Gummel characteristics of SiGe HBT and transfer characteristics of MOSFET are measured before and after irradiation. Base current (IB), leakage current (IOFF) and threshold voltage (VTH) are extracted...
This paper highlights systematic fault isolation approaches to identify back-end of line metal bridging through the combination of techniques such as photon emission, soft defect localization, laser voltage probing as well as combinational logic analysis, to successfully pin point a single metal layer for physical failure analysis, thus boosting the overall success rate and turnaround time.
Thermal effects of the Tm:YAP crystal and the ZGP crystal that used in 5W Mid-infrared solid-state laser are the important factor which affects the laser output characteristic and the reliability. Starting with the thermal conduction function, Tm:YAP and ZGP crystals thermal effects simulation models are build by using finite element simulation technology, the numerical value of the highest temperature...
In this paper, a novel signal toggling technique in Electrical Optical Frequency Mapping/ Phase Mapping (EOFM/EOPM) and Electrical Optical probing (EOF) are performed to successfully localized the fault location and identify the physical defect promptly. A function square wave is asserted into the pin of interest, i.e. leakage pin or the function power pin, for EOFM and EOF purposes. This technique...
SRAM is a major component in semiconductor industry which often requires extensive and exhaustive method of fault isolation, especially for a non-visual defect in a soft failure mode. For these cases, nanoprobing on CA layer is often performed but there are times when it fails to isolate any defect. One reason may be because the failure only occurs at high temperature test environment. This paper...
Corrosion on wafer level aluminium-copper (Al-Cu) interconnects and electroless nickel-palladium (Ni-Pd) pads were characterized using inline metrology and physical failure analysis methods. Chemical methods were then used to study the mechanism of the defects. Al-Cu localized corrosion occurred as Al-oxides growth with the presence of fluorine (F) and chlorine (Cl) due to moisture stain. Using chemical...
Zynq System-on-Chip (SoC) integrates both Processor and Programmable Logic architectures, where the whole functionality of a system is placed on a single chip. Due to the advancement of process technology, the complexity of circuit analysis becomes harder and the failure modes are becoming marginal, e.g., leakage in nano-ampere range. SoC devices require very challenging work for failure localization...
In this paper, analysis of the gate recess variation on DC and RF characteristics on 0.25um psuedomorphic high electron mobility transistor using Sentaurus TCAD simulation have been carried out. Hydrodynamic transport model have been employed for the simulation. Furthermore, off state breakdown characteristics are also exploited, while exploring the essential features of 2-dimensional electron gas...
A previous study on long term reproducibility [1] demonstrated that CAMECA Wf can delivered the relative standard deviation (RSD) of the relative sensitivity factors (RSF) of boron (B) are typically 3.7%. Above results show that deviation can be estimated without testing the standards. This paper will demonstrate that the SIMS RSD depend significantly on the species concentration.
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