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This paper presents a fully configurable and programmable coprocessor IP core to efficiently compute Artificial Neural Networks (ANNs) in heterogeneous System-on-Chips (SoC). There is an increasing interest in moving applications involving streamed data such as those arising in machine-learning systems (machine-vision, speech-recognition, etc.) to highly-integrated low-power embedded devices. In this...
FPGA-based heterogeneous Multiprocessor Systems-on-Chip (HMPSoCs) are becoming quite popular for high performance embedded systems because of their powerful computational ability and relatively flexible architecture to adapt to unexpected system requirement changes. However, with the insatiable demands of supporting an extensive range of applications beyond the limited resources of FPGA chip and shorter...
Field Programmable Gate Arrays are an attractive platform for reconfigurable computing due to their inherent flexibility and low entry cost relative to custom integrated circuits. With modern programmable devices exploiting the most recent fabrication nodes, designs are able to achieve device-level performance and power efficiency that rivals custom integrated circuits. This paper presents the benchmarking...
This paper proposes a 256 Redundant Signed Digits hardware multiplier based on Karatsuba that is suitable for prime field ECC processors. Redundant representation is essential for prime field ECC processors as the basis for carry free arithmetic. The proposed multiplier works by applying Karatsuba method at two levels where three recursively constructed blocks are used to perform large integer multiplication...
Fibre Channel (FC) has been well applied in storage network and avionics environments. It is being implemented as one kind of avionics communication architecture for a variety of next generation aircrafts. However, a challenge engineers have to face is how to realize the complicated FC protocols in a feasible way. So, we propose a design of FC node. It adopts a FPGA module with PCI interface and a...
As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform...
Current chip transistor density enables the design of multiprocessor systems-on-chip (MPSoCs). MPSoCs are an alternative to create complex computational systems because they reduce the cost, area, power dissipation and design time per chip. Due to their complexity and huge design space to explore for such systems, CAD tools and frameworks to customize MPSoCs are mandatory. The main goal of this paper...
Modern FPGA devices can implement a variety of processors with numerous configurable options. Rapid performance estimation of FPGA processors plays a vital role in embedded systems design to select a processor that best fits the application requirements. Traditional performance evaluation techniques such as running the software application on the target processor or using cycle accurate instruction...
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) with manual hardware design. Recent research has demonstrated that soft processors augmented with support for vector instructions provide significant improvements in performance and scalability for data parallel workloads...
The MATMOS Fourier Transform Infrared (FTIR) spectrometer is a concept instrument designed to measure the Mars atmospheric composition using solar occultation from orbit. MATMOS requires high sampling rate (up to 300 kHz), high dynamic range (up to 22 bits) data acquisition to record time-domain interferograms which get converted to spectra on-board the spacecraft. Our previous work presented a system...
Recent improvements in the memory capacity of Field Programmable Gate Arrays (FPGAs) have spurred interest in using the devices for arithmetic floating-point operations. However, adapting a program designed to run on a sequential processor to be run instead on an FPGA can be time-consuming and difficult for anyone lacking significant experience in hardware design. In this paper we use a high-level...
DNA sequence comparison and database search have evolved in the last years as a field of strong competition between several reconfigurable hardware computing groups. In this paper we present a BLAST preprocessor that efficiently marks the parts of the database that may produce matches. Our prefiltering approach offers significant reduction in the size of the database that needs to be fully processed...
The Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Our kiwic compiler takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. In this brief paper, we describe attributes used to mark up I/O nets, embed assertions,...
As FPGA-based systems including soft-processors become increasingly common we are motivated to better understand the best way to scale the performance of such systems. In this paper we explore the organization of processors and caches connected to a single off-chip memory channel, for workloads composed of many independent threads. In particular we design and evaluate real FPGA-based processor, multithreaded...
In this paper we present a trade-off analysis between hardware size and speed performance, measured in clock cycles, concerning fixed-point, memory-based FFT processors designed for FPGA. For OFDM systems using fixed-point FFT processors we also provide bit width requirements for different FFT sizes and digital modulation schemes including QPSK, 16-QAM, 64-QAM, 256-QAM. The information provided is...
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