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The international High Performance Computing community has undertaken the challenge of extreme scale computing — breaking the exaflop barrier in the coming decade. The EU, US, and Japan each have their unique approaches to building machines that can compute the largest scientific and data analysis problems imaginable, from cosmology to climate modeling to personal genomics. However, these extreme...
The Mars Pathfinder landed in the Ares Vallis valley on July 4th, 1997, and after deploying the Sojourner rover and sending back detailed panoramic color photos the mission captured the world's attention and people's imagination. The Mars Pathfinder development was an example of doing design quickly, at less cost and having it work better than expected (give or take a few software “glitches”). So...
Moore's Law continues, but for how long? Many are predicting the end, or at least the slowing, of semiconductor scaling even as FinFETs are being introduced. New technologies, such as 3D integration, offer new opportunities for silicon vendors and customers. These technology trends are converging on Programmable Logic. FPGA vendors are changing the way they build their products and those changes are...
In the last years, partial reconfigurable systems (PRSs) have included Networks-on-Chip (NoCs) as their communication structure. The problem of mapping and positioning in NoCs have been extended to PSRs. Mapping of cores in NoCs aims to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. The placement problem deals with the allocation of those...
Ahstract-Set-wise floating point accumulation is a fundamental operation in scientific computing, but it presents design challenges such as data hazard between the output and input of the deeply pipelined floating point adder and numerical accuracy of results. Streaming reduction architectures on FPGAs generally do not consider the floating point error, which can become a significant factor due to...
This paper proposes an efficient method for implementing parallel AES-GCM cores using FPGAs. The proposed method improves the performance of the parallel architecture (Throughput/Slice). Presented architectures can be used for applications which require encryption and authentication with slow changing keys like Virtual Private Networks (VPNs). Our architectures were evaluated using Virtex5 FPGAs....
Field Programmable Gate Arrays are an attractive platform for reconfigurable computing due to their inherent flexibility and low entry cost relative to custom integrated circuits. With modern programmable devices exploiting the most recent fabrication nodes, designs are able to achieve device-level performance and power efficiency that rivals custom integrated circuits. This paper presents the benchmarking...
Reconfiguration of FPGAs is becoming increasingly popular particularly in networking applications. In order to protect FPGA designs against attacks, secure reconfiguration must be performed. This paper introduces low cost solutions for protecting FPGA designs. This is achieved by implementing low cost hardware architectures of authenticated encryption (AES-CCM, AES-GCM, and PRESENT-GCM) in the static...
This paper presents a promising technique for accelerating frequently executed (hot) code regions. Unlike most accelerators which utilize dedicated hardware structures, our architecture exploits the available execution resources of a chip multiprocessor (CMP), while dynamically specializing into a reconfigurable compute accelerator. Execution units available in one or more general purpose cores are...
Placement is one of the most important techniques in modern field-programmable gate array design. Generally, analytical placement method optimizes the wire-length in global stage while allowing overlaps between blocks and is followed by a legalization step to remove all overlaps. In this paper, we propose a window based legalization method to remove all overlaps and place all instances at legalized...
Dynamic and partial reconfiguration is a well-known technique to update the configuration of a field programmable gate array (FPGA) at runtime. Xilinx FPGAs support this feature which enables extensive research in this domain. However, until today the usage and exploitation of partial reconfiguration has a hurdle. The complex development process, as well as the required control at runtime keeps this...
We apply algorithmic noise-tolerance (ANT) techniques [1] to improve the energy efficiency of DSP circuits implemented on FPGAs. Our approach leverages the programmable power architectural feature in Altera commercial FPGAs that allows internal logic blocks to operate in two modes [2]: high speed or low (leakage) power. We build a main DSP circuit with high utilization of low-power mode blocks, reducing...
The standard way to detect known digital objects inside a stream of bytes consists in using a string matching algorithm initialized with a dictionary containing the objects to detect. Depending on the application, the algorithm may be implemented in software or with dedicated hardware, to speedup the processing. Nevertheless, such approach requires an automaton with a complexity that is linear in...
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