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Bufferless, deflection-routed, Butterfly Fat Trees (BFTs) can outperform state-of-the-art FPGAs overlay NoCs such as Hoplite by as much as 2–5× on throughput and ≈5× on worst-case latency at identical PE counts, and by ≈1.5× on throughput at identical resource costs >16K LUTs for statistical traffic patterns. In this paper, we show how to modify the tree connectivity and routing function to support...
Deflection-routed FPGA overlay NoCs such as Hoplite suffer from high worst-case routing latencies due to the penalty of deflections at large system sizes. Segmentation of communication channels in such NoCs can (1) reduce worst-case packet routing latencies for FPGA traffic, (2) enable efficient composition of multi-application NoC workloads, and (3) ease the burden of supporting Partial Reconfiguration...
Hierarchical routing resources play vital role in FPGA routing. Better routability options can be obtained using segmented approach of wires thus enabling routing optimization. Source and sink logic blocks can be connected via wire segments such that the overall wire length and switching transistors inside the switch box can be saved over an extent. This paper presents an experimental approach of...
In this paper, a novel way to finely tune a net delay on Xilinx Field Programmable Gate arrays (FPGAs) is proposed. It consists of adding floating interconnects (nodes) to the net on which the delay is to be tuned, connected to any input pin of a switch matrix along the net. Adding nodes is made with a TCL script applied to an already placed and routed design. However, such nodes, also called antennas,...
Reconfigurable devices are widely attractive for several application fields thanks to their size, rapid prototyping characteristics, flexibility and upgradability. Thanks to partial Reconfiguration features, FPGA becomes the golden core of the adaptive computation paradigm since they may dynamically change their functionalities based on the elaboration request. Today, adaptive computation is mainly...
Three-dimensional Field Programmable Gate Arrays (3D FPGAs) represent a viable alternative to overcome challenges of integration complexity in modern embedded systems. Mapping applications into 3D FPGAs requires a set of accompanying suite of Computer-Aided Design (CAD) tools. One of critical issue of a 3D FPGA-based implementation is the quality and efficiency of associated CAD algorithms. In this...
This paper proposes to use the high density of vias enabled by monolithic 3D integration to produce multi-stack FPGA designs with improved performance and functionality. The use of fine grain vertical interconnects enables reconfiguration of FPGA logic within a few clock cycles, as shown in our design that features dynamic reconfiguration capabilities through the use of a pair of configuration memories...
We can enhance the performance and efficiency of deflection-routed FPGA overlay NoCs by exploiting the cascading featureof the Xilinx UltraScale BlockRAMs. This allows us to (1) hardenthe multiplexers in the NoC switch crossbars, and (2) efficientlyadd buffering support to deflection-routing. While buffering isnot required for correct operation of a deflection routed NoC, it can boost network throughputs...
Continuous down scaling of CMOS technology in recent years has resulted in exponential increase in static power consumption which acts as a power wall for further transistor integration. One promising approach to throttle the substantial static power of Field-Programmable Gate Array (FPGAs) is to power off unused routing resources such as switch boxes, known as dark silicon. In this paper, we present...
Communications systems make heavy use of FPGAs; their programmability allows system designers to keep up with emerging protocols and their high-speed transceivers enable high bandwidth designs. While FPGAs are extensively used for packet parsing, inspection and classification, they have seen less use as the switch fabric between network ports. However, recent work has proposed embedding a network-on-chip...
Recent research has shown that the integration of a custom-silicon network-on-chip (NoC) into an FPGA fabric can significantly help on-chip communication bandwidth. Although not appropriate for all communication, FPGA hard NoCs provide a scalable infrastructure that will increase in importance as FPGA sizes increase. To date, most FPGA hard NoC implementation has focused on packet-switched routing...
Reducing worst case routing latencies while delivering high throughput and low energy are key design concerns in the engineering of overlay packet-switched NoCs for FPGA fabrics. Deflection routed torus NoCs are known to map particularly well to modern wire-rich FPGA substrates with fracturable LUT organizations while delivering high sustained bandwidths for various workloads and traffic patterns...
In-place Polarity inVersion (IPV) has been proposed to mitigate the single event upset (SEU) induced soft errors for academic VPR FPGA architectures, and this paper extends the original IPV so that it can be used for commercial FPGA architectures. Different from the original IPV, we use a new soft error model based on signal probability and propose a simple yet effective greedy based algorithm. To...
The rapid growth of wire RC delay with technology scaling has put increasing pressure on FPGA architects to make more efficient use of the different layers available in the metal stack. While commercial FPGA architectures have implemented the majority of inter-logic-block wiring on the lower metal layers and a small fraction of wires on the least-resistive upper metal layers, published explorations...
NoC has a significant impact on the power, area and performance of multi-core architectures. The contribution of NoC in the total power budget of a CMP is approximately 30 to 40% [1], and the input buffers of router consume most of it. Therefore, the designers need to design a low power communication architecture of NoC by reducing the power consumption of buffers. In the existing techniques, virtual...
During the last few decades complex programmable circuits have seen a widespread usage in various digital circuit applications. One prominent example are Field Programmable Gate Arrays (FPGAs). Teaching FPGA technology has become an integral part of introductory digital logic courses. However, implementing Boolean functions in this technology requires understanding of several steps that are not trivial,...
Field Programmable Gate Arrays (FPGAs) have proven their potential in accelerating High Performance Computing (HPC) Applications. Conventionally such accelerators predominantly use, FPGAs that contain fine-grained elements such as LookUp Tables (LUTs), Switch Blocks (SB) and Connection Blocks (CB) as basic programmable logic blocks. However, the conventional implementation suffers from high reconfiguration...
We can improve the performance of deflection-routed FPGA overlay networks-on-chip (NoCs) like Hoplite by as much as 10× (random traffic) at the expense of modest extra storage cost when combining static scheduling with packet switching in an efficient, hybrid manner. Deflection routed bufferless NoCs such as Hoplite, allow extremely lightweight packet switched routers on FPGAs, but suffer from high...
Physical Unclonable Functions (PUFs) are a promising way to securely generate and store keys by using the inherent process variations of each chip as a source of randomness. One of the most promising PUFs for FPGAs is the Ring-Oscillator (RO) PUF. In this paper we take a closer look at RO PUFs and their open challenges. Starting from a reference design for a Spartan-6 FPGA based on PUFKY, we show...
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