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Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial...
Integrated Modular Avionics (IMA) architecture provides means for integrating multiple safety-critical applications on a shared hardware in an airborne system. Error free data transfer between different modules of an IMA cabinet is an issue of critical importance. ARINC 659 has proven to be one of the most comprehensive standards for intra-cabinet data transfer within an IMA cabinet of commercial...
We propose an adaptive reliability enhancement structure for deeply-scaled CMOS and future devices that exhibit nondeterministic behavior. This structure forms the basis of a confidence-driven computing model that can be implemented in either a rollback recovery or an iterative dual modular redundancy method incorporating synchronous handshake schemes. The performance and cost of the computing model...
This work presents the design methodology and the optimal FPGA implementation of a hardware video interface that can be used in any embedded system with microprocessors or microcontrollers for direct connection to a VGA compatible monitor. The design level is lowered to schematic details, which offers more optimization possibilities than any hardware description language. Such a visual design was...
As chips have moved from homogeneous single core systems to much more complex, heterogeneous multi-core systems, the ability to create both uniform and efficient operating system services has begun to diminish. The importance of these services suggests that these primitives should no longer be virtual, but rather physical services built into modern computing devices. In this paper we outline some...
In this paper a Globally-Asynchronous Locally-Synchronous (GALS) pipelined processor is implemented on synchronous commercial FPGAs. A simple pipelined accumulator-based processor is implemented as an example for a pipelined processor with varying stages' delays. A novel port controller is designed to ensure the proper operation of the pipeline under any distribution of stage delays. The results show...
The need of critical applications has derived in the development of several techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. This article presents a state of the art in the techniques for reliable microprocessor architectures...
An FPGA-based prototype of a custom high-performance network hardware has been implemented, integrating both a switch and a network interface in one FPGA. The network interfaces to the host processor over HyperTransport. About 85% of the slices of a Virtex IV FX100 FPGA are occupied and 10 individual clock domains are used. Six of the MGT-blocks of the device implement high-speed links to other nodes...
Parallel computing is an important trend of embedded system. One possible response to increasing requirements in computational power is to distribute tasks over various processors and let these processors operate in parallel. Soft-core processors and FPGAs require low Non-Recurring Engineering costs to develop such multi-processors systems. Furthermore, certain FPGAs allow dynamic partial run-time...
An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.
Future chip technologies will change the way we deal with hardware design. (1) logic resources will be available in vast amount and (2) engineering specialized designs for particular applications will no longer be the general approach as the non recurring expenses will grow tremendously. Thus, we believe that online synthesis that takes place during the execution of an application is one way to overcome...
Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance...
The present paper describes a technique for ensuring re- liable softcore processor implementation on SRAM-based field programmable gate arrays (FPGAs), which can handle the effects of single event upsets (SEUs). We propose the triple modular redundancy (TMR) scheme coupled with dynamic partial reconfiguration to remove SEUs from the configuration memory of the FPGA. Although the FPGA is subject to...
Battery-powered sensor nodes call for low power consumption. As a crucial component, a power-efficient sensor network processor greatly reduce the overall power consumption of a node. In the paper, we propose a low-power asynchronous event-driven sensor network processor mapped onto an off-the-shelf clocked FPGA. Since the processor employs a bundled-data asynchronous encoding scheme, we define a...
Multiprocessor platforms are gaining markets as a solution to boost general performance of processor beyond technological limitations that are present in single processors chips, Multi-processor in embedded systems also have a future in particular with applications like SDR(Software Defined Radio) where both high performance and high adaptability are required. Cryptographic algorithms implementation...
Network on chip (NOC) has been proposed for the connection substrate of multiprocessor system on chip (SoC) due to limited bandwidth of bus based solutions. Although some designs are emerging actual design experiences of NOC based multiprocessor system on chip remain scarce contrary to simulation based studies. However, implementation constraints clearly affects th design and modelling of a complex...
In the field of RNA secondary structure prediction, the Zuker algorithm is one of the most popular methods using free energy minimization. However, general-purpose computers including parallel computers or multi-core computers exhibit parallel efficiency of no more than 50% on Zuker. FPGA chips provide a new approach to accelerate the Zuker algorithm by exploiting fine-grained custom design. Zuker...
The amount of time and resources that have to be spent on debugging of embedded cores continuously increases. Approaches valid 10 years ago can no longer be used due to the variety and complexity of peripheral components of SoC solutions that even might consist of multiple heterogeneous cores. In this contribution we show how debugging and tracing of embedded processor cores can be enhanced by use...
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high bandwidth (2.16 Tbit/s), low latency, and flexibility in the processing algorithm. The input data come optically via 1 080 links operating at 2.5 Gbit/s. The whole system is partitioned hierarchically in 18 groups of 5+1 modules...
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