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The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging...
Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defined in the IEC62439-3 about high availability automation networks and proposed as reference network topologies for substation communication networks by IEC61850, assure the upkeep of the communication when an error in a network occurs. Those methods consist in sending information duplicated through different and...
The IEC62439-3: Industrial communication networks - High availability automation networks - Part 3: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defines two protocols which provides zero time recovery against a failure in the network. The first edition of the standard was published in 2010, and two years after a second edition has been published in July 2012...
The IEC62439-3 defines two ways to obtain a high availability automation network: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR). In order to do that, those methods include different paths to send information frames from source to destination and add a redundancy field to the frames. Nodes in the network must remember arrived frames so as to manage the duplicated...
This extended abstract outlines a novel optimization approach for multi-band linear collaborative spectrum (LCS) sensing based on harmony search heuristics. Besides, the description of a centralized system architecture is also included in this manuscript, which is capable of processing the captured spectrum measurements from several nodes in a LCS fashion and storing the decisions made on the spectrum...
The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation...
The work developed has as basis the networks/protocols described in the standard IEC 62439-3 Industrial automation networks - High availability automation networks: PRP and HSR. The similarities of both networks and a software implementation over Linux of PRP protocol have been the starting points taken for this work. A prototype of a HSR node has been developed; this prototype was proved over some...
The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial...
Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based design. Embedded systems have evolved from an uniprocessor to a multiprocessor approach, seeking better performance and less energy consumption. It is widely accepted that Multiprocessor Systems-on-Chip (MPSoC) will become the predominant class of embedded systems in future. In addition, advances in FPGA technology makes...
This paper presents a PCI-Express based platform for the analysis and evaluation of designs that combines Triple Modular Redundancy and Dynamic Reconfiguration to provide Fault Tolerance and Self-repairing capabilities. The paper presents the general architecture of the platform and exemplifies its functionality with the implementation of a Self-Repairing CAN Gateway.
This paper presents a new single event upset (SEU), multiple bit upset (MBU) and single hardware error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional triple module redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing are combined in a dynamically reconfigurable...
In this article a Bus Coupling Unit KNX/EIB standard for Building Automation Systems is presented. The proposed architecture exploits the flexility and computation power of the reconfigurable devices to overcome the limitations of the embedded platform proposed in the standard. Furthermore, the approach takes advantage from the facilities that the new in-system Flash FPGAs provide: a unique code for...
In this article a low-cost KNX-Secure system is presented. It takes advantage from the facilities that the new in-system Flash FPGAs provide: an unique code for each device (DNA) and internal One-Time-Programmable registers. The well known AES-GCM cryptographic and authentication algorithm in combination with a key generated into the FPGA is proposed for the device dependent code ciphering. The modules...
In this paper a multi-platform HDL description of a circuit that implements all the digital processing and RF carrier generation for the class S Power Amplifier proposed by the Institute of Microelectronics and Wireless Systems is presented. The circuit is the combination of a lowpass sigma-delta modulation stage in series with a frequency shifting stage that generates the bitstream that drives a...
A novel cryptographic core (cryptocore) approach for secure communications is presented in this work. It is an AES-Counter Mode core for System-on-Programmable-Devices that takes advantage from the flexibility of the reconfigurable devices. The proposed architecture is parameterizable, so it is easily scalable to fulfill different target area-speed trade-offs. This parametrization affects both the...
In this paper a configurable-system-on-programmable-chip controller for matrix converter is presented. The controller takes advantage from partial reconfiguration to interchange dynamically space-vector-modulation cores with different signal quality-switching power loses trade-off. The internal design is presented and the newest Xilinx design flow for partial reconfiguration is followed to implement...
This paper presents a System-on-Programmable-Chip(SoPC) implementation of the KNX communication standard. KNX is a standardized communication protocol for the automation of homes and buildings. It is an open international standard. This means that any company can freely build new devices to be controlled using the standard. ASoPC implementation of the standard allows for applications of increased...
In this research work we present a reconfigurable platform that implements all the digital processing and RF carrier generation for the class S power amplifier proposed by the Institute of Microelectronics and Wireless Systems. This amplifier is a combination of a lowpass or bandpass sigma-delta modulation stage in series with a frequency shifting stage and a switch mode amplifier followed by a band...
This paper presents a dual core architecture for decompression using the deflate algorithm. The flexibility of the system-on-a-programmable-chips (SoPC) makes possible the introduction of these computationally intensive cores inside a field- programmable-gate-array (FPGA). The proposed architecture is composed of two different cores. One is in charge of the translation of the Huffman codes while the...
DRM (digital radio mondiale) is a new digital audio broadcasting system used in narrow band AM bands. In order to analyze its propagation behavior, high quality receivers must be implemented. Thus, BER and C/N ratios may be measured and analyzed, enabling broadcasters to establish the best strategy to effectively cover a wide geographical area. In this paper, we present such a receiver. This receiver...
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