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The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial...
This work presents the design methodology and the optimal FPGA implementation of a hardware video interface that can be used in any embedded system with microprocessors or microcontrollers for direct connection to a VGA compatible monitor. The design level is lowered to schematic details, which offers more optimization possibilities than any hardware description language. Such a visual design was...
The need of critical applications has derived in the development of several techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. This article presents a state of the art in the techniques for reliable microprocessor architectures...
Battery-powered sensor nodes call for low power consumption. As a crucial component, a power-efficient sensor network processor greatly reduce the overall power consumption of a node. In the paper, we propose a low-power asynchronous event-driven sensor network processor mapped onto an off-the-shelf clocked FPGA. Since the processor employs a bundled-data asynchronous encoding scheme, we define a...
Both standard and windowed watchdog timers were designed to detect flow faults and ensure the safe operation of the systems they supervise. This paper studies the effect of transient failures on microprocessors, and utilizes two methods to compare the fault coverage of both watchdog timers. The first method is injecting a fault while a processor is reading an image from RAM and sending it to the VGA...
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding...
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