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Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level reconfigurable abstractions. Both fine-grain and coarse-grain architectures (e.g. CGRAs) traditionally require low level programming and suffer from long...
Our work1 investigates how to map loops efficiently onto Coarse Grained Reconfigurable Architecture (CGRA). This paper examines the properties of CGRA and builds Map-Reduce inspired models for the loop parallelization problem. We solve our model using Geometric Programming methods to obtain best loop unrolling parameters. Those parameters are used in the Back-End process that followed. Experiment...
Reconfigurable computing in the cloud helps to solve many practical problems relating to scaling out data-centers where computation is limited by energy consumption or latency. However, for reconfigurable computing in the cloud to become practical several research challenges have to be addressed. This paper identifies some of the perquisites for reconfigurable computing systems in the cloud and picks...
This paper provides the first comparison of performance and energy efficiency of high productivity computing systems based on FPGA (Field-Programmable Gate Array) and GPU (Graphics Processing Unit) technologies. The search for higher performance compute solutions has recently led to great interest in heterogeneous systems containing FPGA and GPU accelerators. While these accelerators can provide significant...
In this paper we present an application example for a run-time reconfigurable embedded system. The system design is based on the perceptions of previous works from several groups. We comment on the theoretical background of dynamic reconfiguration with respect to the embedded market and its special needs. Moreover a resource-efficient FPGA system and a first design is presented to serve as a basis...
SRAM based fingerprinting is a promising technique for unique identification of physical devices. This method uses deviations in power-up behaviour caused by the CMOS fabrication process to identify physical devices. In the case of SRAM-based hardware reconfigurable devices such as FPGAs the integrated SRAM cells are often initialized automatically at power-up, sweeping potential identification data...
We present an infrastructure for dynamic reconfiguration of heterogeneous coarse-grained reconfigurable architectures (CGRAs) based on our Gannet SoC platform. We introduce the infrastructure and in particular its domain-specific high-level programming language Gannet-C and discuss the language features that support dynamic reconfiguration and the way they are supported by the compiler and the hardware...
Considering the ability to perform multi-processor architecture systems on FPGA, partial reconfiguration is an opportunity to improve weak soft-core performances by specializing coprocessors according to context-dependent application needs. But at the application level, there is a need for straightforward programming models that allow applications to be easily mapped on an ad hoc architecture without...
We will present a survey of trends in the semiconductor industry for programmable hardware. The main objective of this paper is educational and the focus is FPGAs and its related or vs technologies which have emerged mostly in the second half of the last decade. We will try to analyze what were the prominent reasons for emerging of these technologies. What are the advantages and drawbacks of them,...
The need of non volatility along with the added flexibility of un limited reprogramming like SRAM has lead to the concept of universal memories. MRAM (magnetoresistive random access memory) is one prominent member of them. At present only Flash is providing a limited bridge for that. Flash based FPGAs have several benefits being non volatile but unfortunately also loose many of the features which...
Preemptive multitasking, a popular technique for timesharing of computational resources in software-based systems, faces considerable difficulties when applied to partially reconfigurable hardware. In this paper, we propose a cooperative scheduling technique for reconfigurable hardware threads as a feasible compromise between computational efficiency and implementation complexity. We have implemented...
This paper presents an FPGA implementation of a low cost 8 bit reconfigurable processor core for media processing applications. The core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. This paper presents an investigation of the feasibility of the core as a potential soft processing...
In this paper, a novel reconfigurable architecture, cFPGA (CMOS-Nanorelay FPGA) is developed by integrating carbon nanorelays and CMOS devices to function as FPGA components. cFPGA is a highly efficient architecture, providing 2?? density and standby power improvement along with 30% dynamic power reduction as compared to the CMOS FPGA circuits. This performance improvement is achieved by using 2T1N...
This paper presents a new debugging methodology for applications targeting reconfigurable platforms. The key issue behind is that bringing software engineering techniques advantages to hardware design would reduce design cycles hence time-to-market. Our high-level synthesis framework supports probes insertion both in the behavioural description of the application and in its hierarchical netlist. Probe...
We will explore how processing power of LEON3 processor can be enhanced by connecting small commercially available embedded FPGA (eFPGA) IP with the processor. We will analyze integration of eFPGA with LEON3 in two ways, inside the processor pipeline and as a co-processor. The enhanced processing power helps to reduce dynamic power consumption by Dynamic Frequency Scaling. More computational power...
As field programmable gate arrays (FPGAs) become more widely used, security concerns have been raised regarding FPGA use for cryptographic, sensitive, or proprietary data. Storing or implementing proprietary code and designs on FPGAs could result in the compromise of sensitive information if the FPGA device was physically relinquished or remotely accessible to adversaries seeking to obtain the information...
High performance reconfigurable computers (HPRCs) consist of one or more standard microprocessors tightly coupled with one or more reconfigurable FPGAs. HPRCs have been shown to provide good speedups and good cost/performance ratios, but not necessarily ease of use, leading to a slow acceptance of this technology. HPRCs introduce new design challenges, such as the lack of portability across platforms,...
Many of todaypsilas software-to-hardware compiler projects try to find dataflow parallelism in a sequential program description and use it to generate parallel running hardware components. In this paper we present a new possibility to do a parallel description based on the combination of object-oriented programming and dynamically partial reconfiguration. Our compiler translates software objects directly...
The past decades have witnessed tremendous research efforts devoted to parallel architectures and programming models for natively computing in space. This resulted in systems which comprise a number of processing units ranging from compact Boolean function generators (FPGAs look-up-tables) to full-fledged microprocessors (MPSoCs). It is often stated in the literature of both areas that performance...
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