The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. To avoid significant performance loss through pessimistic over-design new design strategies are required that are cognisant of within-die performance variability. This paper examines the effect of process variability on the clock resources in FPGA devices. A model of...
Customizing the instruction set for particular applications has become a successful practice in the industry in the design of application specific processors. Following the same principle, this paper evaluates the impact of embedding specialized instructions within the processing elements (PEs) of coarse grained reconfigurable arrays (CGRAs). We systematically extract and select regular clusters of...
This paper presents a novel approach to watermark FPGA designs on the netlist level. We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature bits into lookup tables (LUTs). In this way, we tightly integrate the watermark with the design so that simply removing mark carrying components would damage the intellectual property core. Converting functional...
Computational fluid dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive super-computers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using block-RAMs...
This paper proposes a novel test method for measuring the worst case path delay of any circuit on an FPGA, combinatorial or sequential, where little prior knowledge of the circuitpsilas internal structure is required. The method is based on detecting changes in the transition probability profile on the circuitpsilas output nodes while a range of test clock frequencies is stepped through. The method...
A pattern recognition system that can process a large amount of image data at high speed is required in many fields. In this paper, we propose an on-chip pattern recognition system that utilizes the reconfigurability of the FPGA. The features of the system are not only very high recognition speed but also an adaptive function. For example, when objects to be detected change appearance, recognition...
In todays and future automotive electric/electronic architectures the central gateway is one of the key components. The introduction of high performance bus systems like FlexRay and Ethernet, as well as new applications, creates additional requirements for gateway systems. The usage of reconfigurable hardware gives an interesting alternative to existing microcontroller based solutions. A modular gateway...
Understanding the behavior of an application is rarely a trivial task, due to the complexity of the system in which the application is executed, and the complexity of the application itself. The task becomes even more troublesome, if the application is being run in a parallel environment where relationships between each application execution are needed to grasp the necessary understanding of the application...
The constrained operating environments of many FPGA-based embedded systems require flexible security that can be configured to minimize the impact on FPGA area and power consumption. In this paper, a security approach for external memory in FPGA-based embedded systems that exploits FPGA configurability is presented. Our FPGA-based security core provides both confidentiality and integrity for data...
This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Our proposed method provides a simple hardware architecture design, low computation...
This paper presents a novel inversion / non-inversion zero-overhead dynamic optically reconfigurable gate array that can extract good factors from architectures of both optically differential reconfigurable gate arrays and dynamic optically reconfigurable gate arrays. A full VLSI design using a 0.35 mum CMOS process technology is presented. Based on that presentation, three factors are discussed:...
In previously proposed ORGAs, the optical reconfiguration period was designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory differs depending on the number of bright bits included in a configuration context. Therefore, previous ORGAs can not fully exploit reconfiguration performance. For that reason, this paper presents a...
We present new approach to optimize circuits for dynamic reconfiguration in FPGAs. Within a high level synthesis tool we optimize the binding of operations to resources to achieve high re-use of resources and interconnect between different configurations. We demonstrate that reconfiguration costs can be drastically reduced, while adding a small area overhead. Moreover, our method can merge several...
The watershed transformation is a popular image segmentation technique for gray scale images. In this paper, we describe an implementation method of a watershed algorithm based on connected components on FPGA. In the watershed algorithm based on connected components, regular memory accesses by raster scans and irregular memory accesses using FIFO and stack are repeated. The irregular memory accesses...
Currently Xilinxpsilas dynamic partial reconfiguration (DPR) model requires the size and number of partially reconfigurable (PR) regions to be fixed during the design phase. Only one PR module may be active per PR region at any given time. This paper presents a new DPR model that replaces the current multi-PR region model with a single partially reconfigurable domain (PR Domain). Multiple PR modules...
This work presents a novel reconfigurable Galois field multiplier embedded in a dynamically reconfigurable processor for real time programmable Reed Solomon (RS) encoder and decoder targeting various communication standards. The fundamental operation in Reed-Solomon encoding and decoding is the multiplication over Galois field (GF). The reconfigurable GF multiplier with single instruction multiple...
This paper presents an exploration environment for the design of 2D island-style coarse grained FPGA architectures. An architecture description file defines various architectural parameters including the definition of new coarse grained blocks, the positioning of blocks in the architecture and the selection of routing network. Once the initial architecture is defined, a software flow places and routes...
In this paper, we describe an approach for downscaling images for real-time pattern detection on FPGA. Using FPGAs, we can reconfigure specific circuits for given patterns, and detect various patterns efficiently with less hardware resources. In our approach, a sequence of downscaled images (downscaled by alphak (k = 0, 1, 2, ..., n)) is generated, and regions in each image are compared with fixed...
In this paper, aiming toward a compact high-throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage...
We present an FPGA architecture with Time Division Multiplexed (TDM) wiring with hard network routers and use this architecture to implement a circuit switched Network-on-Chip. We compare this network to exiting approaches: either hard or soft implementations of the network on an FPGA. TDM wiring allows us to address the problem of interfacing high-speed hard-routers with slower soft cores. The router...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.