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This paper presents an optimizing methodology for implementing a multi-layer perceptron (MLP) neural network in a Field Programmable Gate Array (FPGA) device. In order to obtain an efficient implementation, a compromise of time and area is needed. Starting from simulation in the learning phase with fixed point operators, we have developed a methodology which allows the automatic generation of a VHDL...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
Pipelining technology can improve clock frequency through shortening the critical path of logic device. However, the complex algorithm of gradient adaptive lattice joint processing (GALJP ) results in its lower work clock frequency. A pipeline optimization approach based on the technology of delay leading transfer is proposed. By approximate treatment to the updated weight coefficients and errors...
In this paper we propose a design methodology to explore partial and dynamic reconfiguration of modern FPGAs. We improve an UML based co-design methodology to allow dynamic properties in embedded systems. Our approach targets MPSoPC (Multiprocessor System on Programmable Chip) which allows area optimization through partial reconfiguration without performance penalty. In our case area reduction is...
This paper presents FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT's Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results...
Recently, FPGAs have been integrated into HPC clusters in order to boost computational performance while reducing power consumption. However, performance and effective logic utilisation is usually limited by the number of inter-device pins and most importantly the interconnection architecture. Mesh interconnection in particular suffers from the pin-limitation problem. The concept of Virtual Wires...
This paper presents a number of approaches to implement decimal multiplication algorithms on Xilinx FPGA's. A variety of algorithms for basic one by one digit multiplication are proposed and FPGA implementations are presented. Later on N by one digit and N by M digit multiplications are studied. Time and area results for sequential and combinational implementations show better figures compared with...
Computers face an ever increasing number of threats from hackers, viruses and other malware; effective Network Intrusion Detection (NID) before a threat affects end-user machines is critical for both financial and national security. As the number of threats and network speeds increase (over 1 gigabit/sec), users of conventional software based NID methods must choose between protection or higher data...
This paper presents a novel approach to watermark FPGA designs on the netlist level. We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature bits into lookup tables (LUTs). In this way, we tightly integrate the watermark with the design so that simply removing mark carrying components would damage the intellectual property core. Converting functional...
Advancement of field programmable gate array (FPGA) faces many challenges. Among the major ones are power management and high speed transceiver I/O demands. To overcome the challenges, process-design co-optimization is required. With co-optimization of process, circuit, and architecture, 45% static power reduction is achieved for a 40 nm FPGA design. With optimized analog devices, high data rate (8...
IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.
Reconfigurable hardware combines the flexibility of software and the efficiency of hardware. Thus, embedded systems can benefit from reconfiguration techniques. Many special aspects of dynamic and partial reconfiguration have been already analyzed. On the one hand reconfiguration is mostly used like a hot-plug mechanism. On the other hand approaches similar to the overlaying technique, known from...
SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavioral SystemC models. Together with Forte Design Systems, a fully automated approach was developed by integrating behavioral synthesis into the design flow. Starting from a behavioral SystemC model, hardware accelerators can...
We show that the VPH tool can accurately model a commercial FPGA on a set of benchmark problems. It is able to model heterogeneous embedded blocks in a hybrid FPGA and facilitates design exploration. This tool combines the benefits of both the VPR and the VEB. VPR allows a larger FPGA architecture design space to be evaluated than commercial tools, and VEB enables analysis of hybrid FPGAs. Current...
In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and comparative genomics. In our initial study, we have targeted a specific application that reconstructs maximum-parsimony (MP) phylogenies for gene-rearrangement data. Like other prevalent applications in computational biology,...
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, we introduce a general polynomial approximation approach with an adaptive divide-in-halves segmentation method for evaluation of LNS arithmetic functions. Second, we develop a library generator that automatically generates...
This paper presents the design and FPGA implementation for different order pulse shaping finite impulse response (FIR) filters. In this paper, the coefficients of the implemented filters have been modified with an optimization algorithm proposed in an earlier work. The use of this algorithm results in reducing the number of non-zero coefficients used to represent the filter's frequency response. Reducing...
Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby...
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconfigurable embedded FPGA cores. This paper presents a multi-objective population based algorithm which given a library of basic blocks and a list of constraints, identifies an optimum reconfigurable embedded reconfigurable...
In recent years, many approaches and techniques have been explored for the optimization of energy usage in wireless sensor networks. Routing is one of these areas in which attempts for efficient utilization of energy have been made. These attempts use fixed (crisp) metrics for making energy-aware routing decisions. In this paper, we have presented the design and implementation of a dedicated fuzzy...
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