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Spatial computing (SC) offers the potential for large improvements in performance and energy efficiency. Many proposed architectures have harnessed these benefits for small kernels. The Tartan architecture attempts to harness these advantages for entire general-purpose applications executing spatially. Previous work on Tartan had a configure-once model of execution, which required prohibitively large...
In this paper we present a new hardware design pattern for improving memory transfers to external dynamic memory in Altera's SOPC-builder tool by reusing the standard DMA IP core for all bulk memory transfers without the need for a CPU. The presented approach doubles the data throughput without the need for extra system resources. In addition it is more effective for choosing optimal clock settings...
The ability of partial reconfiguration of today's FPGAs allows the exchange of dynamic system components at runtime, which enables the realization of self-reconfigurable systems. To ease the design of a partially reconfigurable system this paper presents an integrated design flow for reconfigurable architectures. The design flow includes tools for system partitioning, floorplanning, and automatic...
Reconfigurable architectures and NoC (network-on-chip) communication systems have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting the flexibility of reconfigurable architectures, the run-time adap-tivity through run-time reconfiguration, opens a new area of research by considering dynamic reconfiguration...
Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task clue to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible,...
A temporal correlation based port combination algorithm that customizes the router design in network-on-chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port...
A fundamental objective in the design of a network-on-chip is to minimize its area and power consumption while keeping the performance requirements at acceptable levels. The trade-offs involved in the process depend on the target technology, ASIC or FPGA. This paper presents a novel design approach to customize the routers in a network-on-chip for reconfigurable systems. More specifically, given a...
As CMOS technology scales down into the deep-submicron (DSM) domain, systems on chip (SoC) and especially the interconnect networks (NoC) have become a focus of many research groups in the last years. The complexity, reliability and power consumption of SoCs with hundreds of IP-cores on a single chip is a great challenge for future research. Self organisation and online adaptivity are the key features...
The traditional approach to FPGA packing and CLB-level placement has been shown to yield significantly worse quality than approaches which allow BLEs to move during placement. In practice, however, modern FPGA architectures require expensive DRC checks which can render full BLE-level placement impractical. We address this problem by proposing a novel clustering framework that uses physical information...
An algorithm and architecture for a hardware based simulation accelerator is presented. The accelerator can perform full timing simulation of synchronous digital circuits described at the gate level. The simulator makes use of a cycle based processor core in conjunction with event queues to execute the simulation. By ensuring that the gates are evaluated in rank order, the problem of sorting event...
Sparse matrix by vector multiplication (SMV) is a key operation of many scientific and engineering applications. Field programmable gate arrays (FPGAs) have the potential to significantly improve the performance of computationally intensive applications which are dominated by SMV. A shortcoming of most existing FPGA SMV implementations is that they use on-chip Block RAM or external SRAM to store the...
An FPGA-based approach is proposed for implementing a compression system developed specifically for the signal of phonocardiogram. The compression method offers better rate and distorsion than standard audio compression techniques. Both the algorithm and the details on the solutions adopted for its implementation are presented in this paper.
We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the system, network architecture, MPI library and the parallel image processing library implementations. We validate the performance, scalability and suitability of MPI as a software interface...
In this paper we investigate several common bus architectures and measure effective bandwidth between High Performance Computing cores and off-chip memory. Contributions of this paper include (i) characterizing the behavior of four common organizations using off-the-shelf IP cores, (ii) an investigation of the effect of multiple computational cores sharing the bus structures, and (iii) the development...
The MicroBlaze processor serves in many FPGA designs as the central 32 bit CPU with access to the global off chip memory and peripherals. MicroBlaze provides FSL links for up to 8 coprocessors. We present two MicroBlaze designs. The first design works with 8 PicoBlaze-based accelerators for pipelined, single-precision floating point vector-oriented operations, and delivers over 1.2 GFLOPs. The second...
Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full...
The current generations of FPGA comprise of many specialized hardware cores, like embedded processors, multipliers, RAMs and FIFOs, along with the regular arrays of reconfigurable logic. On any FPGA device, these embedded cores are located at fixed locations only. This makes the task of floorplanning for the applications with heterogeneous components very difficult. Recently, some researchers have...
The new breed of reconfigurable integrated circuits (ICs) offer switched-capacitor based analogue circuits whose functionality can be altered during run-time. Rapidly changing the functionality of an analogue circuit provides interesting opportunities for control systems. It also opens a large design space in which decisions have to be made regarding the frequency and form of reconfiguration. We present...
In this paper we present Minibit+, an approach that optimizes the bit-widths of fixed-point and floating-point designs, while guaranteeing accuracy. Our approach adopts different levels of analysis giving the designer the opportunity to terminate it at any stage to obtain a result. Range analysis is achieved using a combined affine and interval arithmetic approach to reduce the number of bits. Precision...
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