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Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
We present and compare implementations of an affine interior-point algorithm for real-time collision detection on a GPGPU and an FPGA. This particular interior-point algorithm is distinguished from other collision detection methods by its ability to perform detection between pairs of objects undergoing fast rotational and translational movement. This enables inter-frame collision detection, i.e. collision...
Computer architectures are increasingly turning to parallelism and heterogeneity as solutions for boosting performance in the face of power constraints. As this trend continues, the challenges of simulating and evaluating these architectures have grown. Hardware prototypes provide deeper insight into these systems when compared to simulators, but are traditionally more difficult and costly to build...
Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case. This paper describes fully-fledged implementations of single-precision floating point units for a MIPS processor architecture implementation. These coprocessors take as little room as 6% of a medium-sized FPGA, while the processor...
In this paper, we focus on comparison between the complementary logics and masked logics as countermeasures against side channel attacks and we develop AES co-processors to which the countermeasures are applied for this purpose. To evaluate the difference that depends on target devices and process, the co-processors are mounted on 130 nm-ASIC, 90 nm-ASIC and FPGA. Through our performance and security...
Difference-based partial reconfiguration, although simpler to use by not needing previous floor-planning, has its utilization encouraged only for small changes due to its unpredictable nature. This paper proposes a mechanism to avoid this problem by saving the system global state. Therefore it doesn't matter how the difference-based partial bitstream will affect the hardware configuration. This way,...
Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the output which later on will slow down the overall performance. Therefore, the authors proposed a hardware...
A hardware design of a configurable and extensible processor named Tcore, which is based on transport triggered architecture (TTA), is presented in this paper. Due to its flexibility, the Tcore can be used as an application specific processor, especially as a coprocessor for different DSP applications. We have configured Tcore to an instruction level parallel processor to support the application of...
This paper presents a Design Space Exploration(DSE) methodology based on a temporal partitioning strategy for mapping of massive computational dataflow problems into FPGAs. In this approach the FPGAs work as co-processors in a hypothetic reconfigurable computing architecture. The temporal partitioning is based on Tabu Search strategies and libraries of IP-cores. This methodology allows Design Space...
Field programmable gate arrays (FPGAs) become very popular for embedded cryptographic operations. In order to resist side-channel attacks, FPGAs must implement reasoned countermeasures. The most efficient way to mitigate attacks is to adopt a gate-level protection. Two secure gates families exist: those that ldquohiderdquo and those that ldquomaskrdquo side-channel leakage. In this article, we detail...
Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability; while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily...
In this research paper an alternative design for reconfigurable instruction set processor (RISP) has been proposed with the capability of the most optimal configuration overhead for Very Long Instruction Word (VLIW) based architectures. This processor supports the demand-driven modification of its instruction set during the program execution. The processor has been integrated with the high speed partially...
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented...
This work explores how the graphics processing unit (GPU) pipeline model can influence future multi-core architectures which include reconfigurable logic cores. The design challenges of implementing five algorithms on two field programmable gate arrays (FPGAs) and two GPUs are explained and performance results contrasted. Explored algorithm features include data dependence, flexible data reuse patterns...
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