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Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, which distributes the iterations of a loop to be executed in parallel across the available processors. Most of the existing work in this area targets cache based execution platforms...
As embedded and safety-critical applications begin to employ many-core SoCs using sophisticated on-chip networks, ensuring system quality and reliability becomes increasingly complex. Infrastructure IP has been proposed to assist system designers in meeting these requirements by providing various services such as testing and error detection, among others. One such service provided by infrastructure...
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level (RTL) datapath component library and minimizes the leakage delay product (LDP). The proposed...
The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap...
In this paper, we propose a closed form method to evaluate the read stability of an SRAM cell via quartic root finding. By utilizing a simplified MOSFET device model, we model SRAM cell stability by a system of quartic equations. The algebraic nature of the equations along with simplified region boundaries provide the insight that only a few combinations of device operating regions correspond to the...
As the number of transistors on a chip begins to exceed 1 billion and their sensitivity to defects begins to degrade overall yield, it will be mandatory to assign a portion of the transistors for the purposes of built-in- self-test (BIST) and built-in-self-repair (BISR) as part of the supporting circuitry. Here, we focus on the self-test and self-repair of flip-flops (FF's), and their associated interconnect,...
This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically...
Design for manufacturability and yield has becomes a major issue for advanced VLSI technology nodes. The demand for a yield prediction capability has been growing significantly. Unfortunately, systematic yield prediction and analysis is still behind in both research and availability of commercial tools. A major reason for that is the high dependency of such research on hard to come by data from fabs...
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A current- starved voltage controlled oscillator (VCO) is treated as a case study and to the best of the authors' knowledge, this is the first VCO design that accounts for both parasitic degradation and process variation together. The physical...
A novel compact model for subthreshold leakage (Isub) including its extraction scheme has been developed in this paper. Both quantum and stress effects have been covered in this model, and it accurately fits experiment data for both nMOSFETs and pMOSFETs. A study of subthreshold leakage variations (SLVs) for the 65 nm technology has been reported for the first time. Gate length (L) roughness and variations...
In this paper, we propose an efficient statistical analysis method for analyzing on-chip power grids. The new method, called SN-SOR (and its faster version, PSN- SOR), is based on a novel localized relaxed iterative approach and it can perform variational analysis on one node at a time. PSN-SOR further speeds up the analysis by using a refined conditioner, where the initial solution of SN-SOR is used...
Embedded deterministic test is a manufacture test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deterministic stimuli, inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low-cost testers for rapidly achieving high fault coverage, embedded deterministic test must consciously use the...
Test stimulus and response compaction (scan compression) in scan is increasingly becoming an integral part of today's design-for-test (DFT) methodology for achieving high quality test at lower costs. Current generation integrated circuit's (ICs) are very complex designs that produce a large number of unknown values (Xs) during response capture in scan testing. Response compaction techniques have been...
A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is...
Increasing power density (due to faster clock and high device integration density) coupled with limited cooling capacity of the package causes die overheating and leads to reliability concerns. In this paper, we present a methodology to mitigate temperature-induced reliability problems by transferring the heat dissipated in a region of high activity (such as the ALU in a processor that creates localized...
As CMOS technology scales continually, interconnect power has become a significant part of total chip power. Without compromising performance, timing slacks can be utilized to optimize interconnect power efficiently. The optimization of total interconnect power is affected not only by the properties of each interconnect as well as the timing constraint, but also by the circuit topology. In this paper,...
With the advent of ultra deep-submicron (UDSM) regime of integrated circuits, the issues with circuit marginality related transient failures are on the rise. An example of such failures is the thermal hotspot-induced ones, which are common when a particular functional unit experiences high switching activity for a considerable duration. In this paper, we propose an on-line hotspot-induced transient...
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or voltage stress, causes a shift of device parameters, for example threshold voltage Vth, which can also be modeled as a degradation of transistor parameters. Therefore, in order to design circuits, which are robust and reliable,...
We present the statistical SPICE models and associated corner models of passive devices (such as capacitors and resistors) in VLSI semiconductor technologies. The capacitor devices include decoupling capacitors, metal- insulator-metal capacitors (MIMCAPs), junction capacitors, MOS varactors, BEOL metal capacitors, etc. The resistor devices include diffused resistors, silicide blocked polysilicon resistors,...
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