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A hybrid compute system (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. These systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining...
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented...
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