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We present a circuit for strain and vibration sensing from piezoelectric film elements (PVDF). The target application is the monitoring of low-frequency vibration in a biomedical wearable device. Since standard PVDF sensors produce an open-circuit voltage that is too large for direct amplification on an integrated circuit, the circuit performs input signal folding as well as output voltage attenuation...
A compact differential voltage reference cell, which combines an original switched capacitor integrator with a digitally programmable bandgap core, is presented. The two-stage integrator maintains an always-valid output voltage while performing correlated double sampling to effectively reduce the effects of offset and flicker noise. Measurements performed on a prototype designed with the UMC 0.18...
This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by...
Ferroelectric capacitors based on thin films such as lead zirconate Titanate(PZT) and strontium bismuth titanate (SBT) have capacitance density and significant spontaneous polarization. DC-DC switching polarization switching converter is presented in this paper with the utilization of ferroelectric capacitor. The topology used in this converter is series and parallel which is analyzed using calculations,...
In this paper we present a microscale “Smart Dust” type system with a volume of 200 μm × 100 μm × 10 μm, called lablet. The lablet contains a 20 Hz low power clock generator, a sensor, electric actuators and a simple finite state machine to implement a predefined response to the sensor input. The system operates with supply voltages ranging from 0.3 V to 1.8 V and is thus suitable to be supplied from...
This paper describes design challenge in 3D NAND technology and proposes an area- and power-efficient 20V charge pump using multiple tiers for pump capacitors. Using 32 tiers, the pump area and power are respectively reduced by a factor of 4.8 and 1.3 compared to a conventional N-well capacitor pump in 2.5V 3D NAND technology without adding any extra process cost. Charge pump design strategy is also...
An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove...
This paper presents a technique that utilizes comparator timing information to accelerate successive approximation register (SAR) analog-to-digital converter (ADC) conversion process. With the scaling down of power supply voltage, the comparator delay is exponentially increasing. Thus, more information can be potentially extracted from the comparator transient response. In the proposed approach, the...
This paper presents a compact fully-integrated charge pump based voltage doubler for self-powered implantable retinal prostheses. The target input voltage is 0.55 V to meet the output voltage of on-chip photovoltaic cells, and the target output is around 1 V to provide sufficient current for neuron stimulation. Several techniques are adopted in the proposed design, including gate-boosting circuits...
This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact...
A 16-core voltage-stacked IC integrated with a switched-capacitor DC-DC converter demonstrates efficient power delivery. To overcome inter-layer voltage noise issues, the test chip implements and evaluates the benefits of self-timed clocking and clock-phase interleaving. The integrated converter offers minimum voltage guarantees and further reduces voltage noise.
This paper presents a configurable SRAM for low voltage operation supporting both pseudo two-port SRAM (P2P-SRAM) and single-port SRAM (SP-SRAM) functions in one compiler. Unlike conventional pseudo two-port SRAM that always performs read first, this work enables dynamic read-or-write-first selection and write-through function. It can improve SP-SRAM function speed by 90% faster than that of the conventional...
A stepwise-voltage-generation circuit was devised that is based on a capacitor bank and that dissipates no energy when a stepwise voltage is generated. The stepwise voltage is generated spontaneously, and depends neither on the initial voltages to the capacitors nor on the switching order. A new adiabatic-charging circuit based on this circuit was also devised that increases the voltage in a stepwise...
In this paper, an SC voltage doubler-based voltage regulator for ultra-low power energy harvesting applications is presented. It produces a stable 1.2-V power supply, using inputs from 0.63 V to 1.8 V. External compensation and on-chip output capacitor ensure good performance even with zero load current and any load capacitance. The regulator tolerates arbitrary input ramp-ups, and is immune to blackout...
In this paper, the main noise contributors and their effect on single-shot precision are analysed. The TDC analysed here is based on the Nutt method, i.e. the TDC comprises of a clock counter combined with two interpolators, which are either time-to-voltage converters or dual-slope converters. We identify the main noise sources in a time-to-voltage converter and provide analytical estimations of measurement...
This paper presents the design and characterization of a 10 GS/s track and hold amplifier (THA). The circuit was fabricated in a 28 nm CMOS technology. It is based on a switched capacitor approach. At a sampling rate of 10 GS/s, the total harmonic distortion is −38dBc with a 3.75 GHz input signal. The chip includes an active balun and buffer stages for the clock signal and consumes 50 mW, which is...
This paper presents a novel circuit topology to be used with a differential capacitive microsensor. Adopting sampling switches and utilizing modified digital blocks has resulted in a remarkably compact and low-power design. The high linearity in conversion of charge to voltage and the wide range applicability of proposed topology satisfies the design criteria for many applications. The proposed topology...
A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14KB register file (RF) load with an area overhead of 3.6% is demonstrated in 22nm tri-gate CMOS. The all-digital, multi-conversion-mode SCVR provides a wide output voltage range of 0.45–1V from a fixed input voltage of 1.225V. It achieves 63–84% conversion efficiency and supports...
An incremental ADC for Wheatstone CMOS stress sensor systems is described. A switched-capacitors integrator without switches toward virtual ground avoids spur signals, clock feed-through, residual offset and glitches. The circuit, fabricated in a 0.35-μm CMOS technology, consumes 42 μW at 500-kHz clock and 2.8-V supply. Low speed chopping cancels offset and limits the 1/f noise contribution. The signal-to-noise...
A low-power CMOS capacitance-to-digital converter for capacitive sensors array is presented. It consists of a 16-channel MUX, a front-end with wide dynamic range for capacitance-voltage conversion and a novel voltage-pulses convertor. This novel circuit charges the measured capacitor indirectly and converts it into a proportional voltage, and then produces a 16-bits pulses-formed single-line output...
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