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With Network Function Virtualization (NFV) generating significant interest in the network operator community, many network functions, including the LTE EPC, are being built as virtualized software appliances running on commodity hardware, as opposed to custom hardware. To provide fault tolerance and scalable performance, the virtualized network functions are typically built in a clustered architecture,...
The Trustful Space-Time Protocol (TSTP) allows for time synchronization to be performed upon receiving any message from another node in a sensor network, removing the need for explicit synchronization messages. Previous work has shown that TSTP performs well under controlled experimental environments. In this work, we analyze how the quality of synchronization in TSTP is affected when nodes are communicating...
Targeting the development of a silicon carbide (SiC) inverter for electric vehicle/hybrid electric vehicle (EV/HEV) applications, the design considerations of the gate driver for the adopted SiC metal-oxide-semiconductor field-transistor (MOSFET) power modules are presented. Given the system power density requirement, the gate driver design challenges for the commercial off-the-shelf (COTS) SiC modules...
A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed...
With the continuous progress of rural construction, the problem of rural drinking water pollution is increasingly prominent. In view of water pollution, a design of rural drinking water monitoring system based on wireless sensor networks is proposed that nodes take STM32 as the core chip and WLK01L39 as well as its peripheral circuits are used as wireless communication modules and Beidou S1216 is...
In order to ensure the data synchronization between different channels of the same pulse (the first synchronization) and the data synchronization between different pulses of the same channel (the second synchronization) in the pulse acquisition, two design constraints were proposed to ensure the two synchronization. The design constraint of the first synchronized was proposed by hardware structure...
Artificial neural networks are intensively used to perform cognitive tasks such as image classification on traditional computers. With the end of CMOS scaling and increasing demand for efficient neural networks, alternative architectures implementing neural functions efficiently are being studied. This study leverages the demonstrated frequency tuning capabilities of compact nano-oscillators and their...
Multiplexers (MUXes) are ubiquitous in digital circuits. A MUX processes inputs a, b and a select bit s to output a if s = 0 and b otherwise. Hence, in the case of a = b, the output must be a, regardless of s. Unfortunately, common MUX implementations violate that specification if s is degraded. We propose efficient transistor-level implementations of Metastability-Containing Multiplexers (CMUXes)...
The CloudBus protocol is one of the methods which is used for data exchange and concurrent process synchronization in the distributed embedded systems. It realizes decentralized (distributed) control method, where each node is equal to each other. This communication model allows the significant savings in the amount of transmitted data between end modules. However, there are many distributed embedded...
Resiliency, the capability to detect and react after a node failure in the network, is a key element for any network protocol. First, the detection of the failure must be quick to prevent dropping the packets and degrading the throughput too badly. Then, the repair, the computation of another path, has to allow the traffic to reach the destination without too much delay and without increasing the...
The paper presents a method for unknown signal values generation and propagation management during gate level digital simulations of multi-clock circuits. Unknown values occur at outputs of clock domain boundary flip-flops and latches when their timing parameters are violated by input signals and clocks. The method is based on gate level Verilog circuit model transformations. The transformation do...
High-speed cameras are expanding into science laboratories in many disciplines. For example, they can be used for monitoring of the impact testing course, widely spread in evaluation of materials. Usually, they exhibit a slight delay between the trigger pulse was applied and the recording was started. For many applications, this delay may be critical. The authors of this paper have faced two problems:...
A huge upheaval emerges from the transition to autonomous vehicles in the domain of road vehicles, ongoing with a change in the vehicle architecture. Many sensors and Electronic Control Units are added to the current vehicle architecture and further safety requirements like reliability become even more necessary. In this paper we present a potential evolution of the Electrical/Electronic-Architecture,...
We propose an asynchronous-logic (async) Quasi-Delay-lnsensitive (QDI) dual-rail 32-bit Advanced Encryption Standard (AES) Substitution-Box (S-Box) for Differential Power Analysis (DPA) attack countermeasure. There are three novel features in the proposed S-Box. First, the proposed S-Box operates in async QDl protocol with dual-rail data encoding, hence there is only a marginal difference in power...
A major limitation in authenticating passive and remotely powered sensors, tags and cards (for e.g. radio-frequency identification tags or credit cards) is that these devices do not have access to a continuously running system clock. This obviates the use of SecureID type authentication techniques involving random keys and tokens that need to be periodically generated and synchronized. In this paper...
Manual deadlock fixing is error-prone and time-consuming. Exist-ing generic approach (GA) simply inserts gate locks to fix dead-locks by serializing executions, which could introduce various new deadlocks and incur high runtime overhead. We propose a novel approach DFixer to fix deadlocks without introducing any new deadlocks by design. DFixer only selects one thread of a deadlock to pre-acquire a...
A fundamental manifestation of the system-level nature of the modern SOC has been in the explosion of untimed paths on a chip. A single chip is no longer a textbook synchronous entity. Thanks to the use of complex design methodologies like asynchronous clock domains, interacting dynamic power domains, aggressive dynamic reset schemes, the wide-spread use of timing exceptions, GALS etc., large swaths...
Metastability in digital circuits is a spurious mode of operation induced by violation of setup/hold times of stateful components. It cannot be avoided deterministically when transitioning from continuously-valued to (discrete) binary signals. However, in prior work (Lenzen & Medina ASYNC 2016) it has been shown that it is possible to fully and deterministically contain the effect of metastability...
The primary advantages of stochastic computing are the very simple hardware required to implement complex operations, its ability to gracefully tolerate noise, and the skew tolerance. Its relatively long latency, however, is a potential barrier to widespread use of this paradigm, particularly when high accuracy is required. This work proposes a new, high-speed, yet accurate approach for implementing...
This paper analysis and compares the different driving techniques for the brushless DC motors (BLDC). First, the conventional block commutation technique used to drive the BLDC is discussed with respect to the produced torque ripple. Second, the modified techniques like the overlap and phase advance techniques discussed as well. Finally, a combined driving technique including the phase advance and...
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