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A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed...
The run-pause-resume (RPR) debug methodology allows one to pause the normal circuit operations, observe the internal states of flip-flops and then resume the normal operations for further debug process. Data invalidation is a major problem that needs to be addressed when debugging a multiple-clock design with this methodology. This problem occurs when flip-flops in a receiving clock domain capture...
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