The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Cloud computing has become an attractive computing paradigm in recent years to offer on demand computing resources for users worldwide. Through Virtual Machine (VM) technologies, the cloud service providers (CSPs) can provide users the infrastructure, platform, and software with a quite low cost. With the drastically growing number of data centers, the energy efficiency has drawn a global attention...
Physical Unclonable Function (PUF) has now become a core lightweight hardware-intrinsic cryptographic primitive for device identification and authentication to secure edge computing in Internet of Things (IoT). The main challenge in most delay-based PUF implementations is the rival of response uniqueness and reliability. Due to routing constraint, implementation of delay-based strong PUF on FPGA tends...
Local layout effects create pattern dependencies at the 16nm node and below that make prediction of functional and parametric yield increasingly challenging. For logic design, precharacterizing all possible neighboring patterns is impractical due to exponential complexity, and silicon characterization is practically impossible. In this paper we propose a virtual characterization vehicle (VCV) methodology...
This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410...
Directed Self-Assembly is the method by which a self-assembly polymer is forced to follow a desired geometry defined or influenced by a guiding pattern. Such guiding pattern uses surface potentials, confinement or both to achieve polymer configurations that result in circuit-relevant topologies, which can be patterned onto a substrate.
Recording electroencephalography (EEG) in multiple mice within one cage is needed not only to allow high throughput testing, but to also maintain normal social and behavioral cues when studying sleep, memory and psychiatric disorders. This work proposes a concept and a blueprint of implementation of a low-power, untethered, fully integrated, implantable system suitable for EEG applications. The system...
Emerging non-volatile memory (NVM) technologies with computation capabilities can be effectively leveraged for computing tasks on resource-constrained Internet of Things (IoT) nodes. Redox-based Resistive RAM (ReRAM) is a promising NVM technology due to its high density, low leakage power and ability to perform functionally complete set of Boolean operations. The secure transmission of IoT sensory...
Microprocessors and FPGAs need to enable simpler and compact platforms via integration of self-contained test and training circuits, training of data interface buffers for process and temperature variation being a prime example. This paper studies package embedding of resistors for buffer tuning and presents a scheme to utilize a single resistor to train a large number of buffers without increase...
In this paper, an ultra-low-leakage 2T1C compact SRAM is proposed using Tunnel FETs (TFETs). Proposed design utilizes negative differential resistance property of TFETs and capacitor leakage to implement 1T1C latch. Additional 1T read port is added for reading to avoid data stability issues during read operation. Proposed SRAM design is scalable and easily adaptable for lower technology nodes. Ultra-low...
Making a computing system that mimic biological neural behavior in mammalian brain has attracted worldwide attention and endeavor. Neuromorphic computing systems, employing very-large-scale integration circuits to implement onto hardware, incorporates learning. Neural encoder, as one of the crucial component in neuromorphic computing systems, encodes the input information into spikes. By taking the...
In advanced technology nodes, BEOL interconnect stack geometry has become a key lever for design enablement. The rapid increase of interconnect RC leads to not only performance loss from interconnect delay increase, but circuit power and area degradation as well. Thus, optimization of BEOL dimensions (i.e., wire width, spacing and thickness subject to a given layers pitch constraint) is crucial to...
Ring Oscillator (RO) Physical Unclonable Function (PUF) is one of the most popular silicon PUFs which exploit manufacturing variations during the chip fabrication process. RO PUF can generate secret bits by comparing the frequency difference between two ROs. However, previous RO PUFs improve flexibility and reliability through adding redundant ROs and thus incur unacceptable hardware overheads. In...
Accurate hold time analysis of sequential cells is crucial to high performance enterprise server microprocessor circuit design. Due to tight timing margins, process variation, and increased instance counts of latches and flops in a microprocessor, fast and accurate hold time analysis with process variation consideration is needed. In this article, we present a novel, high-sigma, SPICE-based analysis...
We present our methodology in applying a well established statistical dynamic power prediction technique in a production environment to an embedded commercial ‘scalar and vector processor’. The pitfalls faced and solutions to guide the statistical solver to build a low error power prediction model are discussed. In our proposed method, we extracted stall probe-points in a processor, used selective...
In the era of post-device scaling, three-dimensional (3-D) integration is a promising solution to meet performance, power, and cost requirements in modern applications, such as IoT, high performance computing, and cyber-physical systems. A novel design automation flow, compatible with static timing analysis (STA), for exploring the timing and power of 3-D ICs is proposed. Among the different types...
Accurate timing characterization of flip-flops is critical for robust circuit design. Conventionally, setup time and hold time are characterized independently, which results in pessimistic/optimistic designs. To reduce this pessimism/optimism, the interdependency between setup/hold-time has to be taken into account. Fast and accurate characterization of the setup/hold-time interdependency is however...
Debugging logic functions involves finding the function of some of the internals nodes such that their functionality becomes correct, according to the given specification. In some cases, different new inputs are required for those internal nodes to be able to correct the functionality. In this paper, we propose an efficient method for selecting inputs of internal nodes during debug such that correction...
Write-erase cycling of flash memories has distinct failure signatures that have been thoroughly documented in the literature. A new mechanism has been uncovered when cycling at low temperatures. On the 65nm embedded flash technology, units exhibited a programming failure signature. However, further investigation verified that fail bits were fully programmed. Cause of failure was attributed to a non-classical...
Fault injection attack against embedded devices has attracted much attention in recent years. As a highly efficient fault injection, EM fault injection (EMFI) outperforms other injection means owing to its outstanding penetration capability in incurring local faults into security ICs. In this paper, we present an all digital countermeasure for detecting the on-the-fly EMFI attempts in silicon chips...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.