The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A super-pixel based on-chip compression is proposed in this paper. The compression is achieved by reading only one sample for each super-pixel. The proposed technique and the corresponding circuit are simulated in MATLAB and UMC 180 nm CMOS technology, respectively. Higher values of PSNR are observed as compared to the state-of-the-art on-chip compression techniques. For the compression factor of...
Post-silicon validation is concerned for discovering design errors that escape to the silicon prototypes. Recent research efforts have shown how to reuse the constraints from pre-silicon verification to support post-silicon constrained-random validation. The objective is to subject the prototype to a large volume of random, yet functionally-compliant stimuli. In this paper, we present a new method...
Generally, VLSI Circuits are very complex due to the technology scaling. Post-silicon validation is a critical part of Integrated Circuits. It is the process of finding the bugs that have escaped from the pre-silicon phase. According to International Technology Roadmap for Semiconductors (ITRS), time-to-market is the major constraint for verification and testing. The main challenge of post-silicon...
Static compaction procedures reduce the number of tests or test cubes in a given test set, thus reducing the test data volume and test application time. In the context of test data compression where on-chip decompression is based on a linear-feedback shift-register (LFSR), this paper describes a static compaction procedure that is applied directly to the LFSR seeds. This procedure provides an option...
To effect a low-reflection interconnect between GSG probe pads and on-chip GCPW, a linear taper between the signal pad and the GCPW signal line is often included. This work evaluates, both in parametric simulation and experimentation, the effect of this taper shape to the input reflection in the band 1 – 110 GHz. It is found that, although longer tapers offer some advantage below 30 GHz, the taper...
In this paper, multi-objective design of integrated spiral inductors is investigated. The method aims at finding the best possible trade-offs between inductor size and its quality factor. We adopt a penalty function approach to achieve a required inductance at a given operating frequency. The design process exploits a Pareto front exploration technique with trust-region-embedded gradient search as...
This paper reviews historical development of on-chip electrostatic discharging (ESD) protection designs for ICs. ESD failure is the biggest reliability challenge to ICs. On-chip ESD protection is the core for integrated design-for-reliability (iDfR), which is required for the advanced ICs and microsystems. This review discusses the past, current and future of on-chip ESD protection designs.
Successful power supply noise mitigation requires a system-level approach that includes design and modeling of the mitigation circuits with the power delivery network (PDN) on the chip, the chip module, the backplane, and the voltage regulator module (VRM). Traditionally, periodic square-wave activity patterns with all cores in sync, which yield low-frequency (LF) or mid-frequency (MF) impedance peaks...
Formal verification techniques for System-on-Chips (SoCs) have matured significantly over the last years. They can penetrate deeply into a design to exhibit complex functional dependencies between various design components in terms of detailed logic and temporal relationships. The purpose of this paper is to show how this knowledge can be leveraged to optimize the dynamic power consumptions of SoC...
For modern complex designs it is impossible to fully specify design behavior, and only feasible to verify functionally meaningful scenarios. Hardware Trojans modifying only unspecified functionality are not possible to detect using existing verification methodologies and Trojan detection strategies. We propose a detection methodology for these Trojans by 1) precisely defining “suspicious” unspecified...
A double-π equivalent circuit model well-fitted for on-chip inductors with GaN process is presented in this paper. The equivalent circuit is made up of two cells and can feature the frequency-dependent characteristics well in a wide range of frequency up to 20GHz. The parameter extraction is conducted based on the improved characteristic function method according to four parts. The validation includes...
High dV/dt immunity is desired for isolated gate driving of next generation fast switching power devices. This requires the on-chip isolation transformer to have a small capacitive coupling between the coils. Therefore, in this paper, on-chip transformers with solid ground shield (SGS) and patterned ground shield (PGS) structures are proposed and studied. Simulation results show that the SGS achieves...
In this paper, on-chip interconnects based on Cu-single-walled carbon nanotube (SWCNT) composite are studied using transmission line model. The transfer function is obtained and approximated by a linear parameter expression. The relative stability analysis of Cu-SWCNT composite interconnects is carried out by the Nyquist criteria.
Security is becoming an essential problem for integrated circuits (ICs). Various attacks, such as reverse engineering and dumping on-chip data, have been reported to undermine IC security. IEEE 1149.1, also known as JTAG, is primarily used for IC manufacturing test but inevitably provides a "backdoor" that can be exploited to attack ICs. Encryption has been used extensively as...
Due to the compact layout of millimeter-wave integrated-circuit, the effects caused by coupling among neighboring inductors may seriously degrade circuit performance. This paper presents two kinds of spiral inductor including a stand-alone inductor and an adjacent-inductor pair which are both fabricated with the 0.13-µm CMOS process. Improved equivalent circuit models of the two kinds of inductors...
The noise induced by variations in power supply adversely effects System-on-chip (SoC) performance and these effects could be understood through modelling and analysis of Power Distribution Network (PDN). This paper presents modelling of PDN by incorporation of BGR and LDO for analyzing the effect of supply induced noise on the PDN performance. The effect of Simultaneous Switching Noise (SSN) resulting...
Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount of data in faster and more efficient ways than ever before. At the same time, reducing power noise and designing dense traces become a challenging part of the design processes. In particular, high signal density on a package naturally restricts the resources for robust power delivery when keeping the...
Power integrity of integrated circuits (IC) becomes more important due to increasing dynamic current with lower supply voltage. However, we cannot perform the power noise analysis when using IC internal voltage regulator module (VRM) in present common tools. To predict practical voltage drop, the simulation model should include accurate on/off-chip power distribution network and internal voltage regulator...
A substrate coupling analysis and simulation flow for high frequency CMOS system on chip design is presented. It's a straightforward method that can be directly adopted by designers as it only requires commercial design tools. Full chip level simulation including substrate, interconnect parasitics and package is provided in any stage of the design process. A 5 GHz CMOS LNA in the presence of an 88...
On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.