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This paper presents a high-efficiency, linear power amplifier (PA) for 28GHz mobile communications in 40nm CMOS technology. The design and layout are optimized for high linearity while maintaining high gain and output power. A capacitance neutralized differential pair with source degeneration inductor for linearity enhancement is discussed. The inductive degeneration technique greatly increases the...
A 30mW Full-Band-Capture receiver based on harmonic selection is presented. The prototype receiver employs a 32-phase non-overlapping LO, and is capable of simultaneously receiving multiple wireless signals arbitrarily located between 600MHz and 3GHz. The receiver achieves 2.4 to 5dB NF and tolerates more than −10dBm out-of-band blockers. A digital harmonic rejection calibration is also proposed to...
We present a stacked-FET monolithic millimeter-wave (mmW) integrated circuit Doherty power amplifier (DPA). The DPA employs a novel asymmetrical stack gate bias to achieve high power and high efficiency at 6-dB power back-off (PBO). The circuit is fabricated in a 0.15-µm enhancement mode (E-mode) Gallium Arsenide (GaAs) process. Experimental results demonstrate output power at 1-dB gain compression...
A dual-band power amplifier (PA) with an integrated reconfigurable transformer is presented. The PA operating in the S/X-band is fully integrated using a 0.18-µm RF CMOS process. The switchable transformer is designed by tuning its primary winding and a shunt capacitor at 50Ω load with passive efficiency more than 62%/67% for S/X-band. The measurement results show saturated output power (PSAT) of...
An ULP back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the 3rd harmonic of the LO for power efficiency. The LP-65nm CMOS receiver consumes 335µW with a sensitivity of −72dBm at a BER...
This paper presents a wakeup receiver for latency-critical IoT applications in 90nm CMOS, which is fully compliant to many popular IoT wireless standards with constant envelope modulations, such as Bluetooth Low Energy and IEEE802.15.4. Paired with a standard-compliant transmitter, the proposed wakeup receiver method minimizes the overhead in system power, area and complexity. The proposed 2-dimensional...
An ultra-wideband sub-THz signal generation system is proposed for rotational spectroscopy employing a magnetic-tuning varactor-less quad-band voltage-controlled oscillator (QB-VCO), a locking-range-enhanced dual-mode injection-locked frequency divider (DM-ILFD), a power-efficient injection-locked oscillator (ILO) as a driver, and sub-THz mixers with frequency multipliers for frequency extension....
Following the race for transmitting/receiving at higher data rate, we can observe intensive development of millimeter-wave wireless systems in low-cost CMOS technology. Data rates above 10 Gb/s are now targeted in order to address the data traffic bottleneck of backhaul links for the 5G wireless network. To do so, antenna-systems operating at sub-THz frequencies show great potential, leveraging high-performance...
This paper presents a 32-element phased-array architecture suitable for fifth-generation (5G) communication links. A 28–32 GHz silicon core chip is designed with 4 transmit/receive elements each with 14 dB gain control, 6-bit phase control, 4.6 dB measured noise figure (NF) in the RX mode and 10 dBm output 1 dB compression point (OP1dB) in the TX mode. Eight of these chips are flipped on a low-cost...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and a fully-digital polar transmitter is presented. For the receiver, a current-mode RF front-end covers the mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains and bandwidths with an automatic gain/DC-offset calibration. Implemented in 40nm CMOS with 1V supply, this...
A highly linear power amplifier (PA) with ultra-wide video bandwidth is designed at a Ka-band for 5G application. To get a high linearity with high efficiency, a deep class-AB topology with 2nd harmonic control circuits is employed, reducing the 3rd order nonlinearity. Further, an efficient low-drop out (LDO) regulator is proposed to suppress the memory effect generated by the envelope and fundamental...
A wideband, local Power Amplifier (PA) linearization technique is presented. The proposed Adaptive Gain and Phase Adjustment (AGPA) local linearization technique compensates for both AM-AM and AM-PM distortion of PA for large channel bandwidths of hundreds of megahertz. A 60GHz PA designed in a 28nm CMOS process is designed and measured. AGPA improves the OP1dB of the stacked PA by 2.8dB from 9.5dBm...
In this work, a high voltage (HV) galvanically isolated chip-to-chip communication circuit utilizing laterally coupled resonators is reported. The adjacently placed resonators provide high voltage galvanic isolation (GI) using horizontal space between resonators filled with oxide, which minimizes the need for thick inter-metal dielectrics. A previously unexplored application for lateral coupling is...
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