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Layout design principles of IP blocks in the IC, and frequency mixers in particular, are discussed. Several variants of the layout design are carried out. They are modeled and compared to a schematic implementation. Qualitative assessment of implementations is carried out. The conclusions and the ways of improvement are proposed. The nature and the origin of deviations and variations in the process...
We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance...
In highly-scaled CMOS technologies, analog and digital functionality are often combined into more powerful systems. Implementation of any complex digital circuit requires digital synthesis and therefore a digital standard cell library. Absence of the digital libraries in core design kits provided by the foundries is a significant hurdle for academic institutions to design complex electronic systems...
A fully integrated K-band two stage 16-way power amplifier was designed and fabricated in 0.18-um CMOS technology. By using the direct shunt combining method, the matching networks and combining networks can be designed simultaneously, and this realizes the combining possibility of sixteen power unit cells. At the same time, some design skills and layout techniques are proposed to reduce the DC bias...
This paper presents the Application Specific Integrated Circuit (ASIC) design of a Digital Pulse Width Modulation (DPWM) signal generator, for the implementation of PWM control signal generator, to be integrated on a single die with the single-stage input-powered bridge rectifier with boost switch (BRBS) DC boost converter, in view to eliminate the need of external PWM control signal generator, while...
A fully integrated K band high power amplifier was designed and fabricated in 0.18 um CMOS technology. Some design and layout techniques are proposed to reduce the DC bias complexity of this 8-way combined high power amplifier. The measurement result shows that this amplifier achieves 20 dBm saturation output power, 6 GHz 3-dB bandwidth, and flat gain response from 20.4 GHz to 24.1 GHz.
We propose a new layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. In order to understand the impact of parasitics in monolithic 3D-stacked CMOS circuits, careful analysis of intra- and inter- layer parasitic capacitances were performed by using physics-based RC extractor for realistic 3D structure. As a result, we found that separation...
Current status is presented for the development and experimental verifcation of 0.18 μm high voltage CMOS integrated circuits with pad-based ESD protection made with the use of lateral bipolar transistor. Developed I/O pads provide 2000 V ESD protection.
In this paper an area and power efficient 56T 4-bit comparator design has been presented by using GDI technique. The proposed 4-bit comparator design consist of 28 NMOS and 28 PMOS. A GDI full adder module has been used to design this comparator which consumes less area and power at 120 nm as compared to previous full adder designs. The proposed 4- bit comparator design is based on this area and power...
Circuit designing using CMOS logic is the promising field for VLSI engineers, but with demand of small and portable devices, new techniques for low power are emerging. This paper proposed four different 10-T subtraction logic using Gate Diffusion Index (a new technique for low power design). Simulation results are performed using 180nm technology using Cadence Virtuoso. Complete verification for performance...
A 10 bit cryogenic current steering D/A converter (DAC), operating from room temperature to as low as 4.2K temperature, is presented here. The converter is primarily designed for a Silicon (Si) quantum computer controller circuit for initializing quantum bits (qubits). A new analog calibration method with an on chip reference current generator is applied to all the bits of the converter to overcome...
Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates...
The results on SEE sensitivity of 0.5 µm SOI CMOS microprocessor are presented and discussed. The comparative analysis of different test techniques (particle accelerator, pulsed laser technique and 252Cf fission source) is provided for the cache. The possible sources of discrepancies between test results and the ways of data correction and methods of testing techniques' accuracy improvement are discussed.
The successful scaling of CMOS technology through many generations has carried with it an implicit assumption that the most effective geometries for assembling circuits does not change significantly. As the ability to scale the physical dimensions becomes increasingly difficult in patterning and process, this assumption no longer leads to an optimal solution. This paper reviews a pragmatic process...
A fully differential 60 GHz three-stage transformer-coupled amplifier is designed and implemented in 65 nm digital CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanisms, and simultaneous input/inter-stage/output matching networks are used to facilitate a compact circuit design. With a cascoded circuit configuration, the amplifier is tested...
The primary objective of this study is to explore the connection of the device physics in the Boltzmann-Heisenberg limits and the parameters of the digital circuits implemented from these devices. We offer an abstraction of a Minimal Turing Machine built from the limiting devices and circuits, thus Turing-Heisenberg Rapprochement. The analysis suggests a possible limit to computational performance...
Low power multipliers with high clock frequencies play an important role in today's digital signal processing. In this work, the performance analysis of Wallace-tree, Array and Baugh-Wooley multiplier architectures is carried out. Physical verification of all the sub-blocks is performed using HSpice to check their functionality and to optimize for low power by using transistor sizing. The layouts...
A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65 nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2 mm2 while the ADC core area is 0.16 mm2.
We present the first experimental report of dose-enhancement effects due to interconnects in deep-submicron CMOS, using ad-hoc designed MOSFETs with different metal layouts. We demonstrate that the presence of metal-1 tracks in the proximity of the device active areas may significantly modify the response to X-rays. The impact of the secondary electron emission from metal-1 layers is strongly dependent...
A 1.2 V 12 b 30 MS/s pipelined ADC, implemented in a 65 nm standard CMOS technology, achieves an SNDR of 65.1 dB with a rail-to-rail 4.7 MHz input. A capacitive reference scaling technique is proposed to alleviate the high gain requirement of the opamp and a wide input range of 2.4 Vp-p differential for low voltage operation in the nanometer domain. The prototype ADC dissipates 18 mW and occupies...
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