The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We propose an arrayed test structure to assess the damages of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed under back-side LSI processes, such as by Focused Ion Beam (FIB). Back-side process with FIB is becoming essential to analyze and repair modern LSI chips, to avoid processing through many metal layers with dense wiring and dummy patterns. To access transistors from back-side,...
This paper reports a normally-off high voltage hybrid Al2O3/GaN gate-recessed MOSFET fabricated on silicon substrate. The normally off operation was implemented by digital gate recess using an oxidation and wet etching based AlGaN barrier remove technique. The Al2O3/GaN MOSFET features a true normally off operation with a threshold voltage of 2 V extracted by the linear extrapolation of the transfer...
Electrical performances of ultra-short channel MOSFETs were investigated on SOI substrates. The channel length was scaled to 3 nm using the anisotropic wet etching technique. A difficulty of junction technology was solved by fabrication of Junctionless-FET, which consists of uniform high concentration dopants through the body of device. Superior Junctionless-FET performance was confirmed when the...
The embedded strain gauges in a PQC-TEG were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. In addition, the fluctuation of the process such as the intrinsic stress of thin films...
For the past years, MEMS-based devices such as Suspended Gate Metal-Oxide-Semiconductor Field-Effect Transistor (SG-MOSFET) and air-gap poly Si Thin-Film Transistors (TFTs) have received considerable attention because of their abrupt switching characteristics which is attractive for solving the non-scalable subthreshold swing (SS) of traditional MOSFETs. Although some simulation results showed that...
This work presents a process to fabricate FinFETs in bulk silicon with advancements in critical fabrication steps such as STI trench oxide recess and adjustment of fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to...
We present the fabrication and the testing of self sensing submicron thick piezoresistive cantilevers. Two kind of piezoresistive transducers (piezoresistor and MOSFET transistor) are integrated into the cantilever in the (100) direction, by n-type implantation (As). Cantilevers with both types of transducers are successfully fabricated, showing a yield of 100% and a standard deviation in the electrical...
A simple top down method to fabricate an array of vertically stacked nanowires is presented. By taking advantage of the non-uniformity of the Inductive Coupled Plasma (ICP) etching process to form a scalloped sidewall followed by a subsequent stress limited oxidation step, a narrow silicon fin can be vertically patterned to form stacked nanowires with different cross-sectional shapes. The stacked...
The Vt variability in scaled FinFETs with gate length (Lg) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall...
This paper presents a highly scalable π-shaped source/drain (π-S/D) quasi-silicon-on-insulator (SOI) MOSFET and summarizes its preliminary characteristics compared with the recessed S/D SOI MOSFET and international technology roadmap for semiconductors (ITRS) roadmap values. SiGe-Si epitaxial growth, Si and SiGe etching, growth of epitaxial Si, and selective SiGe removal are used to form the π-S/D...
The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths. Especially, the LER of nanowires, which contains two...
Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ~946 ??A/??m at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated as a result of core/shell...
FinFETs with 1 mum tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins...
We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional...
In this work, we present a novel vertical MOSFET with embedded gate structure and try to overcome the challenges mentioned above by modifying the junction depth. Therefore, four types of vertical sidewall MOSFETs with embedded gate (EVGMOS) are also demonstrated and called the EVGMOS having lightly-doped drain (LDD) w/o or w/ 2.5 nm Si etching after gate formation and non-LDD w/o or w/ 2.5 nm Si etching...
This work focuses on FinFETs with high aspect-ratio and thus a wide MOSFET channels in each fin, which translates into higher device density per chip area and more efficient use of the silicon real-estate. Moreover, in analog applications where multi-fin devices are required for wider transistors, a small number of taller fins is preferable to a large number of shorter fins in terms of gate resistance...
A new trench-planar gate MOSFET (TPMOS) structure is proposed, in which the shallow trench filled with n-type polysilicon is located at the center of n-drift region between two p-type regions. Compared with conventional VDMOS, the new structure's on-resistance can reduce about 25%, the breakdown voltage can increase 10% and switching loss can retain immovability. Furthermore, the shallow trench structure...
For the first time, an analytical model of an Accumulation-Mode Suspended-Gate MOSFET is proposed. For very low power operation, adhesion energies of gate and gate oxide as low as 130 muJ/m2 are required as well as sub-2.3 N/m doubly clamped gate. Experimentally a 0.2 N/m suspended silicon nanowire was processed, opening perspectives for device downscaling.
The potential of bulk silicon with classical gate oxides and poly silicon gate electrodes has not come to its end yet. This paper discusses the possibility to produce conventional MOS-Transistors on bulk silicon in the deep sub-50 nm-region with extreme low demands to the used substrate and process equipment. A process that uses a modified local oxidation of silicon technique with low and high frequency...
This publication presents a novel combination of nanoscale silicon field emitters fabricated by focused ion beam implant, subsequent etching and integrated extractor to carry MOSFET-controlled behavior required for future lithography applications. A control range of 2 decades is presented with up to 10 nA of emitted current per array at extraction voltages as low as 10 V. A special focus was put on...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.