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In many communications applications semiconductor devices operate in a pulsed mode, where rapid temperature transients are continuously experienced within the die. We proposed a novel junction-level cooling technology where a metallic phase change material (PCM) was embedded in close proximity to the active transistor channels without interfering with the device's electrical response. Here we present...
We present the reliabilities in compressively strained SiGe channel pMOSFETs. A Si capping layer in SiGe channel pMOSFETs improved the negative bias temperature instability (NBTI) without device performance degradation. Also, the Si capped device exhibits the better NBTI reliability than the Si channel device. Because a Si capped structure forms the double barrier layer in the interface, it is the...
A numerical investigation of electrical and thermal properties of a lateral trench field-plate (TFP) LDMOS is proposed. Beside the advantage in terms of specific on-resistance (RSP) vs. breakdown voltage (VBD) trade-off, achieved with a proper optimization of the geometrical and doping parameters, the use of deep trenches is discussed here with particular attention to their impact on the electrical...
NBTI reliability of buried SiGe channel p-FETs is investigated as a function of Ge concentration, SiGe layer thickness and Si cap thickness. Measurements show that NBTI reliability can be dramatically improved by varying these three parameters, i.e., increasing the Ge fraction, increasing the thickness of the SiGe layer, and reducing the Si cap thickness. Consequently, it is demonstrated that SiGe...
This paper aims to investigate the performance and reliability trade-off of the self-aligned (SA) pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) field-effect transistors (FETs). Based on the simulations, the S/D-tie effects are crucial to the future of quasi-SOI devices. The preliminary results of electrical characteristics of the SA-piFETs are carefully demonstrated.
High-speed FIB silicon trenching is used to remove substrate materials around large structures on semiconductor devices. After removing the surrounding substrate material, it is possible to perform FIB cross-sectional analyses on structures that would normally be too large for such an approach. Through-silicon-vias (TSVs) are examined in detail, but other applications are also briefly described.
A self-isolating, lateral IGBT device with high voltage blocking capability (>700 V), high on-state current density (150 A/cm2 at Vds=4 V) and very fast turn-off (< 50 ns), realized in membrane on bulk Si technology is reported here. The device has been manufactured using a standard 5 V, 0.35 mum bulk CMOS process on 8" wafers with the addition of two masks: i) n-drift for the HV blocking...
For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance...
In this paper, a 40 V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18 mum LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici. The process complexity to incorporate the HV kept as simple as possible which does not affect much due to baseline. DOE model are constructed from both the critical...
This paper presents the results of extensive simulations on the characterization of asymmetrical channel device, namely Dual material Gate Fully Depleted Silicon On Insulator (DMG-FD-SOI) in the sub-100nm dimensions with emphasis on the analog, radio frequency (RF) performances and short channel effects (SCEs). The obtained results may serve as useful guidelines to get a basis overview of this gate-material...
Negative bias temperature instability (NBTI) in PMOS has emerged as one of the critical reliability concerns in deep sub-micron devices. A comprehensive study has performed to improve the device NBTI performance by process optimization. It is found that the most effective ways to reduce the NBTI degradation are to control the nitrogen concentration and profile in the nitrided gate oxide, to implement...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
In this paper, for the first time, a novel devise-architecture namely multi-source/drain SOI MOSFET is proposed and compared with a conventional SOI MOSFET. According to the simulation result, our proposed transistor not only maintains the desirable short channel behaviour, but also enhances the on/off current ratio due to the multi-source/drain scheme.
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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