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We comparatively investigated the impact of layout and trench on four types of field oxide Pch MOSTs in a thick film SOI technology with due consideration to isolation trench. High blocking capability (~20 V per um of drift length) for both off- and on- state breakdown voltage close to 300 V, along with reasonable high temperature reverse bias ruggedness, has been experimentally realized with minimum...
The integrated power technologies intends to integrate devices and functions in Moore's law with the ones in More-then-Moores directions. The technology, where integrating power MOSFET together with high quality passive analog component and high speed digital processor is possible, requires effort to enhance analog and high V low Ron MOSFET in process and design support. The advantage of foundry technology...
The commercialisation of new concepts in power devices and electronics through formation of start-up companies is discussed. Two companies in which the author has been associated as a founder are examined as examples. One a fabless semiconductor IC company in the area of power management, and the other an inverter company in which IC technology is coupled with novel power electronics at the module...
We report on the experimental demonstration of a novel n-channel GaN epilayer RESURF GaN MOSFET with good trade-off between breakdown voltage and specific on-resistance for the first time. Device with 4 mum channel length and 16 mum RESURF length has breakdown voltage up to 730 V with specific on-resistance 34 mOmega-cm2 (VG-VT=20 V).
During Short-Circuit (SC) operations, strong current oscillations of IGBTs can appear. Simulation studies also confirm this. No parasitic inductances are required for such oscillations. A simplified equivalent circuit of the device, which is basically an RC oscillator, is able to reproduce the oscillations. The occurrence of oscillations depends on the model parameters, which can be related to the...
The Future Renewable Electric Energy Delivery and Management (FREEDM) Systems Center is a National Science Foundation (NSF) Generation-III Engineering Research Center (ERC) established in 2008 with the mission to develop the fundamental and enabling technologies necessary for a new and paradigm shifting power grid infrastructure, the FREEDM System. This paper will highlight the role of power electronics...
This paper presents ESD protection structure with novel trigger technique for LDMOS based on BiCD process. The proposed ESD protection element includes the same structure as drain region in Nch-LDMOS, the vertical NPN transistor and the lateral NPN transistor. The trigger voltage is depended on the breakdown voltage in the drain region integrated in ESD protection device and the avalanche current...
Numerous techniques have been used to improve the voltage handling capability of high voltage power devices with the aim to obtain the breakdown of a plane junction. In this work, a new concept of low cost, low surface and high efficiency junction termination for power devices is presented and experimentally validated. This termination is based on a large and deep trench filled by BCB (BenzoCycloButene)...
We experimentally demonstrate a super-junction LDMOS transistor in a 0.18 mum BCD technology. The buffered super-junction structure is implemented by the use of existing N- and P-drift layer, which are optimized for conventional 20 V to 30 V LDMOS transistors. The breakdown voltage and the specific on-resistance of the fabricated super-junction LDMOS are 98.6 V and 1.01 mOmegaldrcm2, respectively...
We have researched breaking the trade-off limitations between the overall loss and the reverse recovery softness of High Voltage (HV) freewheeling diodes. For the first time, our results show that the oscillatory phenomena in the reverse operation for HV diodes originate in the enlarging behavior of the space charge region to the cathode side during reverse operation and the extracting hole velocity...
This paper describes for the first time the determination of transient transistor capacitances of a high voltage transistor in a commutation circuit with application relevant conditions. Therefore, the gained characteristics reflect the transistor capacitances during switching. The dependency on operating conditions can be analyzed. New information on the drain current distribution between channel...
In this paper, we introduce a fully functional high voltage (Vrrm = 4.5 kV) and high current (IFM= 7 kA) p+p-n-n+ diode based on radiation enhanced diffusion (RED) technology. The RED-Diode employs a low-doped p-layer buried at ap100 mum to increase the dynamic avalanche ruggedness for high SOA capability. The diode was processed on a 100 mm wafer and can safely turn off 4 and 7 kA @ 140degC @ 1500...
GaN smart power chip technology has been realized using GaN-on-Si HEMT platform, featuring monolithically integrated high-voltage power devices and low-voltage peripheral devices for mixed-signal functional blocks. Two imperative functional blocks for smart power applications with wide-temperature-range stability are demonstrated. The first one is a voltage reference generator, and the second one...
Analyzing the dynamics of current filaments is essential for a correct understanding of SOA limitations. Current filaments can occur during the reverse-recovery period of p+-n--n+ diodes. In this work, we apply the results from an analysis of the plasma-front dynamics for the one-dimensional case to conditions under which current filaments appear in the depletion layers due to dynamic avalanche. We...
This paper presents an integrated digital class D audio power amplifier output stage implemented in a 40 V, 0.35 mum HV-CMOS technology. The integrated output stage consists of a full H-bridge, gate drivers, bootstrap diodes and protection circuits. Its performance was found to be better than previously published output stages implemented in SOI based BCD processes, which are typically more complex...
This paper demonstrates that degradation mechanisms can be controlled by electric field tuning with Dielectric RESURF (STI -Shallow Trench Isolation- interleaves in the drain extension) and lateral field plates (gate fingers on top of the STI regions). Transistors, rated for max. Vds=5.5 and 20 V, show on-resistance (Ron) of 6.5 and 40 mOmegamm2 respectively (comparable with optimized devices [1,...
We have developed a monolithic isolator that provides an isolation voltage of 4 kV and a signal transmission rate of 100 Mbps. Two circuit areas are isolated using 34 trenches on a bonded SOI with 3-mum-thick buried oxide. The inequality in the voltages applied to the trenches is reduced using polysilicon resistors parallel to the trenches, which increases the isolation voltage from 2.4 to 4.0 kV...
The low-loss self-driven rectifier we developed requires no external power supply and uses a novel CMOS control circuit that generates the power MOSFET drive signal by boosting the intrinsic body diode voltage drop. The rectifier significantly improved conduction loss - a 47% decrease from intrinsic-body-diode-based conduction loss - during half-wave rectification. It can replace with a common diode...
This paper presents a novel technology for automatic driving of the passive PMOS to improve a Lateral-IGBT switching performance. Though the former technology, which we had introduced, has very simple driving circuitry, it still needs some additional process or structural change. The novel technology eliminates these remained problems without decrease in device performance. Simulation results indicate...
Understanding self-heating effect is essential in order to analyze and model the performances of high power transistors. In this paper a new test structure to model thermal coupling on multi-fingered devices is proposed. This structure allows extracting thermal coupling coefficients between different sources. Applied in the case of NLDEMOS devices on SOI technology, a basic model for these coefficients...
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