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In this paper, the effects of nanowire (NW) line-edge roughness (LER) in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) are investigated by 3-D statistical simulation in terms of both performance variation and mean value degradation. A physical model is developed for NW LER induced performance degradation in SNWTs for the first time. The results indicate large performance mean value degradations...
A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs...
In this study, the influence of composition of thin films on the interface integrity between a hafnium dioxide thin film and a gate electrode was investigated by using a quantum chemical molecular dynamics method. Effect of the fluctuation of the composition around the HfO2±x/metal interface on the formation of the interfacial layer was analyzed quantitatively. Post-oxidation annealing after deposition...
We present a new algorithm for the exact solution of the system of equations describing charge trapping and transport across the dielectric stack of nitride-based charge trapping memories. The algorithm is implemented in a physical MANOS model accounting for temperature effects and charge trapping into the Al2O3 blocking layer. The model reproduces threshold voltage shifts measured at different temperatures...
The interconnect scaling and the introduction of new processes and materials raise an issue of justifiability and applicability of phenomenological continuum-level models. The parameters of continuum-level electromigration models are averages over values which generally vary on microscopic and atomistic scale. Therefore it is necessary to investigate under which conditions these microscopic or atomistic...
Memory elements existing and under research are compared for their suitability in computer memory applications. Cross point arrays of phase change elements with matched isolation devices are found to be particularly attractive and the challenge to model them is analyzed.
We use a newly developed three-dimensional electrothermal Monte Carlo simulator, using finite-element meshing, to study metal-insulator field-effect transistors (MISFETs) based on a single InAs Nanowire. The model involves the coupling of an ensemble Monte Carlo simulation with the solution of the heat diffusion equation, and is carefully calibrated with data from experimental work on these devices...
Statistical variability (SV) is one of the fundamental limiting factors for future nano- CMOS scaling and integration of. Variability aware design is essential to achieve reasonable yield and reliability in the manufacture of circuit and systems. To develop effective variability aware design technologies it is essential to have a reliable and accurate statistical compact modeling strategy. In this...
We theoretically investigate the gate voltage dependence of the interaction between modulated acoustic phonons and electrons in SiO2-coated Si nanowires. The gate voltage decreases the form factor calculated with modulated acoustic phonons as well as that for bulk phonons. However, the relative difference between the two form factors, that is, the phonon modulation effect on the form factor becomes...
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