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We study the interface properties of 4H silicon carbide Si-face (0001) and a-face (1120) power MOSFETs using the charge pumping technique. MOSFETs produced on the a-face show a higher electron mobility than Si-face devices, although their charge pumping signal is 5 times higher, indicating a higher interface/border trap density. We show the main contribution to the interface/border trap density on...
Noise measurements are efficient for interface trap density characterization in MOSFETs and can be extended to bare silicon-on-insulator wafers. A physical model to explain the experimental results will be presented. The impact of measurement parameters, like die area and probe distance, is discussed comparing experimental and calculated characteristics. Important clarifications concerning the effective...
In this paper, we characterize the interface properties of In-rich In0.65Ga0.35As and In0.75Ga0.25As MOSFETs with ALD Al2O3 gate dielectric. Interface trap density is extracted from physically based quantum mechanical low frequency CV model. We show that donor-like traps dominate the Dit profile for In0.75Ga0.25As-channel compared to In0.65Ga0.35As-channel MOSFETs. This result explains the reason...
In this paper, current noise in the charge-transfer device fabricated by 65-nm bulk CMOS process, having different gate oxide thicknesses is reported both under direct current (DC) and charge transfer (CT) mode of operations. The interface trap density in these gate oxides were also estimated using charge pumping technique. Optimized gate oxide thickness for reduced noise power in the CT operation...
In this paper, we have investigated bulk trap and interface trap density (Dit) caused by millisecond annealing (MSA) using gate current fluctuation (GCF) and charge pumping measurements. We show that the high energy flash lamp annealing (FLA) creates the GCF with a long duration time and it is critical issue to get a stable SRAM operation. FLA creates interface traps localized at the gate edge of...
The performance and reliability of ZrO2/In0.53Ga0.47As MOSFETs are shown to be improved by simultaneous reduction of dielectric and interface charges. An amorphous (La)AlOx interlayer at the ZrO2/In0.53Ga0.47As interface is a key to reduce border traps, interface traps and move ZrO2 fixed charge away from the In0.53Ga0.47As. Border traps are reduced ~3x, effective fixed charges are reduced ~3x and...
The highest electron mobility in Ge NMOS to-date, ~1.5 times the universal Si mobility, is demonstrated experimentally. Gate stack engineered with ozone-oxidation is integrated with low temperature S/D activation to fabricate Ge NMOS. Mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analyses for...
The effects of stress polarity in bias-temperature instability (BTI) tests on high-?? gate dielectric stacks were studied based on the distribution of interface traps and bulk traps extracted by modified charge-pumping (CP) techniques. The bipolar bias-temperature instability were compared between MOSFETs with HfO2/LaOx and HfO2/AlOx dielectric stacks. From the results of interface trap density (N...
This paper compares device performance for In0.53Ga0.47As MOSFETs using single HfO2 gate dielectric with stacked gate dielectrics using various interfacial layers between HfO2 and In0.53Ga0.47As substrate including Al2O3, HfAlOx, LaAlOx, and LaHfOx. Of the gate stacks studied, Al2O3/HfO2, HfAlOx/HfO2, and LaAlOx/HfO2 bilayer gate dielectrics exhibit lower subthreshold swing, higher drive current and...
The main focus in this study is the ability to determine the CNL in Ge, defined as the crossing point where acceptor and donor-like trap densities are equal. We find CNL ~0.14 eV above the valence band edge, in good agreement with previous reports [3, 4], which locate it at 0.1 eV. The low-lying CNL is one of the essential reasons for negative charging of Ge surfaces, positive threshold voltage shift...
We report the results of a systematic study to understand low drive current of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (rhoc), which are comparable (or symmetric) for both n- and p-MOSFETs. Effective...
Through a combination of measurement techniques, we study the interface properties of In0.65Ga0.35As transistor with ALD deposited Al2O3 gate dielectric. We show that the interface trap density at In0.65Ga0.35As/Al2O3 interface can be relatively high, but the transistor still exhibits inversion characteristics. A detailed profiling of the interface traps shows that majority of the interface traps...
The fabrication of Germanium-On-Insulator (GeOI) by wafer bonding and ion-cut approach was investigated. With cyclic HF/DIW cleaning and N2 plasma surface activation, large-area layer transfer of GeOI substrates was realized by ion-cut processes with bulk Ge wafer as the donor wafer. The GeOI substrates are thermally stable up to 550??C annealing and surface roughness can be smoothed down to 0.3 nm...
Negative bias temperature instability in pMOSFETs with thermally and plasma nitrided oxides is investigated using quasi-DC Id-Vg (slow Id-Vg) and on-the-fly interface trap (OFIT) measurement methods. By comparing the OFIT results with those observed from Id-Vg measurements, we found that the threshold voltage shift measured by slow Id-Vg is mainly due to the interface trap since the oxide charge is...
The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of germanium-on-insulator pMOSFETs is shown using the Lim & Fossum model historically developed for fully depleted SOI devices. The doping and the thickness of the Ge film do not change significantly the top interface trap density. The bottom one is slightly raised by doping the Ge film. This method can be...
With the decrease of the high-k layer thickness, NBTI becomes more critical than PBTI. The relative contribution of interface states and trapping on NBTI is analysed in Hf-based stacks. Dit density and generation kinetics were found to be similar to that in SiO2, whereas a very large fast trapping component was evidenced. The pre-existing traps responsible for this fast trapping effect were related...
In this paper, an analytical model of subthreshold swing for the double-gate accumulation-mode P-channel SOI MOSFET is described. The model is based on Poisson's equation and depletion approximation, and the relation of the subthreshold swing with both the gate oxide capacitance and the interface trap density is obtained. The model is verified by experiment and by numerical simulation. Also an approach...
I-V characteristics of PD (partially-depleted) NMOS transistors with GAA (gate-all-around) structure fabricated on SIMOX which is hardened by silicon ions implantation were discussed under total-dose irradiation of three bias conditions. It is found experimentally that irradiation-induced threshold voltage shift DeltaVth and leakage current of hardened transistors was greatly reduced, comparing to...
In this paper, the dynamic negative bias temperature instability (DNBTI) characteristics of p-MOSFET with N-plasma SiON dielectric are studied. Under dynamic stress, the nearly consistent frequency dependent characteristics of threshold voltage shift (DeltaVth) and interface trap density (DeltaNit) were observed. The results show that the degradation and recovery of DNBTI are still dominated by the...
Spontaneous recovery of threshold voltage and channel carrier mobility in DC gate bias stressed power VDMOSFETs, as well as the underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. A chain of mechanisms related to a presence of hydrogen species is proposed to explain the observed changes of oxide-trapped charge...
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