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This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0...
These tutorials discuss the following: Integrated LC oscillators; Embedded Memories for SoC: Overview of Design, Test, and Applications and Challenges in the Nano-Scale CMOS; Ultra Low-Power and Low-Voltage Digital-Circuit Design Techniques; Layout - The Other Half of Nanometer Analog Design; DPLL-Based Clock and Data Recovery; Practical Power-Delay Design Trade-offs; Distortion in Cellular Receivers;...
This paper presents a novel digital calibration technique for pipelined ADCs, which compensates both sub-DAC and interstage gain error. The proposed calibration technique is very efficient comparing to other existing calibration techniques, in which only additions and subtractions are employed in this algorithm, no multiplication and division is included. The simplicity of the calibration makes it...
Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-threaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the...
Energy efficiency plays an important role in the design of high performance analog CMOS circuits. In medium- to high accuracy circuits, it is becoming increasingly difficult to maintain energy efficiency as CMOS technology is scaled to nanometer dimensions. This paper discusses some of the important challenges often faced by analog designers working with nanoscale CMOS technologies and reviews state-of-the-art...
In this paper, we propose an efficient approach to reduce the effect of the Simultaneous Switching Noise (SSN) for mixed System on Chip (SoC). In order to validate the approach, we have designed a 14-bits 100MHz pipeline ADC as an example. Finite Element Method (FEM) and Method of Moment (MoM) are chose to do the electromagnetic extraction of package and bond-wires separately. The proposed approach...
This paper presents a method for modeling chip-package resonance using impulse response and for measuring waveforms under varying conditions. We evaluated chip-package resonance with the following variations in conditions: (i) with and without on-package capacitors; (ii) differing positions on the chip; (iii) differing points of observation outside the chip (probe points for the package capacitor...
In this paper, in order to reduce the power consumption of a cyclic ADC, for different cycles in digitizing an analog input sample, the values of the capacitors are scaled down. The power consumption of the operational amplifier is adaptively reduced as well. In order to demonstrate the effectiveness of the proposed technique, a 1.8V 12-bit 104kS/s ADC has been designed in a 0.18μm CMOS technology...
A 16-channel sensor amplifier was designed in the Jazz 0.18 ??m CMOS process. The sensor amplifier has programmable gain from 20 to 2000 and a DC offset cancellation of ??0.3 V using bulk voltage control. A charge pump, band gap reference and a resistor string DAC were designed for bulk voltage control. Input referred noise of 0.465 ??V was achieved at a gain of 2000. The power required per channel...
In this paper, a high-resolution medium-frequency single-loop fourth-order 1-bit sigma-delta modulator is implemented in 0.18 ??m CMOS technology. The modulator has been presented with an oversampling ratio of 50, clock frequency of 31.25 MHz, 312.5 kHz bandwidth, and achieves a peak SNR of 101.7 dB, which is 16.6-bit resolution, 103 dB dynamic range. The whole circuits consume 58.55-mW from a single...
Signal and power integrity in electronic design is not an easy subject to teach as it involves both electrical circuit and electromagnetic field as well physical structure of active and passive components. Great effort has been made to develop teaching and evaluating materials for the subject in engineering schools, especially at undergraduate level. This paper describes our work on the development...
This paper describes a power and area efficient pipeline ADC design. This ADC was designed in 65 nm process without any special mask requirement and can work with supply voltage of 1.3 V consuming 10 mW providing 9.7 ENOB at 80 MSPS while occupying less than 0.2 square millimeters.
Ground bounce noise (GBN) is becoming one of the major challenges for designing high speed system and packages. It causes serious signal integrity (SI) problems in the high speed system. Traditional techniques center on adding more decoupling capacitors to create a low impedance path. Electromagnetic band gap (EBG) structure is used to suppress GBN combined with decoupling capacitors in this study...
High end networking and computing applications continue to drive silicon technologies for higher data rates and increased bandwidth. The push for silicon performance also drives a need for packaging performance to deliver clean and efficient power to the device. This paper compares the electrical performance of three new advanced packaging technologies designed to improve the DC and AC power delivery...
We present a combined LNA-mixer circuit with low area and low power, for the 2.4 GHz ISM band. The circuit has two versions: one has an output RC low-pass filter suitable for low IF frequencies; the other has an output LC band-pass filter suitable for medium IF frequencies. Circuits, with IF of 50 MHz and 400 MHz, were designed using UMC 0.13 mum CMOS technology and 1.2 V supply, and dissipate approximately...
This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on gm/ID concept is manipulated in the synthesis process. With the proposed design automation...
DC/DC Converters are now an essential part in a system due to the various needs of supply voltage that is necessary for different circuits in the system. However, there are many papers which have dealt for efficiency or for a novel structure that would be customized to the specific design, but few dealt with the noise characteristics of DC/DC converters which could critically affect to the output...
In this paper, a wideband LC cross-coupled VCO is designed and realized with the TSMC 0.18 mum CMOS technology. By incorporating band switching capacitors, the overall tuning frequency range is divided into 16 bands, covering 1.17-1.9 GHz (47%). A linear time variant (LTV) model is used to quantitatively analyze voltage biased oscillators. In order to minimize the phase noise, the size of the MOSFET...
Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling capacitor (decap) allocation is one of the most effective way in reducing serious dynamic power noises (hotspots). To allocate decap before placement, we observed that not only locations but also rising time of functional cells...
A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5 ??m CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded)...
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